From: lkcl <lkcl@web>
Date: Sat, 29 Oct 2022 22:51:55 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~26
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=589945ce01bb3f8f9f82faf4dd7f90a7a26c6443;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls003.mdwn b/openpower/sv/rfc/ls003.mdwn
index 1bcb0fb2d..d2ce0380e 100644
--- a/openpower/sv/rfc/ls003.mdwn
+++ b/openpower/sv/rfc/ls003.mdwn
@@ -249,7 +249,7 @@ Examples:
 divmod2du r4, r0, r1, r2
 ```
 
-# Dynamic-Shift Left Doubleword
+# Double-Shift Left Doubleword
 
 `dsld RT,RA,RB,RC`
 
@@ -259,11 +259,11 @@ divmod2du r4, r0, r1, r2
 
 Pseudo-code:
 
-    n <- (RB)[58:63]                        # Take lower 6-bits of RB for shift
+    n <- (RB)[58:63]                        # Use lower 6-bits for shift
     v <- ROTL64((RA), n)                    # Rotate RA 64-bit left by n bits
-    mask <- MASK(64, 63-n)                  # 1's mask, set mask[64-n:63] to 0's
-    RT <- (v[0:63] & mask) | ((RC) & ¬mask) # Mask out bits
-    RS <- v[0:63] & ¬mask                   # ?
+    mask <- MASK(64, 63-n)                  # 1's mask in MSBs
+    RT <- (v[0:63] & mask) | ((RC) & ¬mask) # mask-in RC into RT
+    RS <- v[0:63] & ¬mask                   # part normally lost into RC
     overflow = 0                            # Clear overflow flag
     if RS != [0]*64:                        # Check if RS is NOT zero
         overflow = 1                        # Set the overflow flag
@@ -272,26 +272,21 @@ Special Registers Altered:
 
     CR0                    (if Rc=1)
 
-**CHECK if overflow flag is the expected behaviour**
-
 The contents of register RA are shifted left the number
-of bits specified by (RB) 58:63.
-**Please check if this is correct!!! This condition is taken
-from PowerISA spec page 253, definition of MASK128(x,y)!!!**
-A mask is generated having 0-bits from bit (64-n) through
-bit 63 and 1-bits elsewhere.
-
-The rotated data is ANDed with the generated mask, and ORed
-with contents of RC ANDed with inverted mask.
-The result is placed into register RT.
+of bits specified by (RB) 58:63. The same number of
+shifted bits are taken from register RC and placed into
+the LSBs of the result, RT.
+Additionally, the MSB bits of register RA that would normally
+be discarded by a 64-bit left shift are placed into the
+LSBs of RS.
 
-Additionally, the rotated data is ANDed with inverted mask and
-placed into register RS. If value in RS is not all 0's, the
-overflow flag is raised.
+*Note: When Rc=1, and the value in RS is nonzero,
+the overflow flag is raised in CR0.*
 
-Similarly maddedu and divmod2du, dsld can be chained (using RC).
+*Programmer's note:
+similar to maddedu and divmod2du, dsld can be chained (using RC).*
 
-# Dynamic-Shift Right Doubleword
+# Double-Shift Right Doubleword
 
 `dsrd RT,RA,RB,RC`