From: Eddie Hung <eddie@fpgeh.com>
Date: Sun, 12 Jan 2020 01:25:32 +0000 (-0800)
Subject: write_xaiger: create holes_sigmap before modifications
X-Git-Tag: working-ls180~872
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=58ab9f6021bc5b90956d97759ef0f3bc8c7e209e;p=yosys.git

write_xaiger: create holes_sigmap before modifications
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 7ee5058ae..a6c87159d 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -771,6 +771,8 @@ struct XAigerWriter
 				//   created a new $paramod ...
 				Pass::call_on_module(holes_module->design, holes_module, "flatten -wb; techmap; aigmap");
 
+				SigMap holes_sigmap(holes_module);
+
 				dict<SigSpec, SigSpec> replace;
 				for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) {
 					auto cell = it->second;
@@ -808,7 +810,6 @@ struct XAigerWriter
 					++it;
 				}
 
-				SigMap holes_sigmap(holes_module);
 				for (auto &conn : holes_module->connections_) {
 					auto it = replace.find(sigmap(conn.second));
 					if (it != replace.end())