From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 2 Dec 2018 09:03:47 +0000 (+0000)
Subject: add MESI cache implementations
X-Git-Tag: convert-csv-opcode-to-binary~4822
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=58b3a45b9b6cf4644547723ef9eb38f28578b18e;p=libreriscv.git

add MESI cache implementations
---

diff --git a/3d_gpu/microarchitecture.mdwn b/3d_gpu/microarchitecture.mdwn
index 665dde99a..7922e1897 100644
--- a/3d_gpu/microarchitecture.mdwn
+++ b/3d_gpu/microarchitecture.mdwn
@@ -113,6 +113,8 @@ called the flip-flops orchestrating the timing "collectors".
 * <https://en.wikipedia.org/wiki/Reservation_station>
 * <https://en.wikipedia.org/wiki/Register_renaming> points out that
   reservation stations take a *lot* of power.
+* MESI cache protocol, python <https://github.com/sunkarapk/mesi-cache.git>
+  <https://github.com/afwolfe/mesi-simulator>
 * <https://en.wikipedia.org/wiki/Classic_RISC_pipeline#Solution_A._Bypassing>
   pipeline bypassing
 * Register File Bank Cacheing <https://www.princeton.edu/~rblee/ELE572Papers/MultiBankRegFile_ISCA2000.pdf>