From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 28 May 2020 12:26:21 +0000 (+0100)
Subject: extra check on rd.req in test_alu_compunit
X-Git-Tag: div_pipeline~761
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=58d2d830f087c5edecbbf68ea24336c622ff9149;p=soc.git

extra check on rd.req in test_alu_compunit
---

diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py
index 3b2dc1ec..1be45181 100644
--- a/src/soc/fu/compunits/test/test_alu_compunit.py
+++ b/src/soc/fu/compunits/test/test_alu_compunit.py
@@ -19,12 +19,18 @@ def set_cu_input(cu, idx, data):
     yield cu.src_i[idx].eq(data)
     while True:
         rd_rel_o = yield cu.rd.rel[idx]
-        print ("rd_rel %d wait" % idx, rd_rel_o)
+        print ("rd_rel %d wait HI" % idx, rd_rel_o)
         if rd_rel_o:
             break
         yield
     yield cu.rd.go[idx].eq(1)
-    yield
+    while True:
+        yield
+        rd_rel_o = yield cu.rd.rel[idx]
+        if rd_rel_o:
+            break
+        print ("rd_rel %d wait HI" % idx, rd_rel_o)
+        yield
     yield cu.rd.go[idx].eq(0)