From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 15 Feb 2020 12:55:32 +0000 (+0000)
Subject: reduce bitwidth of intermediate output
X-Git-Tag: ls180-24jan2020~160
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=58ebb74afbd545a477ef078fd7c3c94347460bda;p=ieee754fpu.git

reduce bitwidth of intermediate output
---

diff --git a/src/ieee754/part_shift/part_shift_dynamic.py b/src/ieee754/part_shift/part_shift_dynamic.py
index 99b602f9..cf83f1ac 100644
--- a/src/ieee754/part_shift/part_shift_dynamic.py
+++ b/src/ieee754/part_shift/part_shift_dynamic.py
@@ -142,10 +142,11 @@ class PartitionedDynamicShift(Elaboratable):
         out.append(result[s:e])
         for i in range(1, len(keys)):
             start, end = (intervals[i][0], width)
+            reswid = width - start
             result = partial_results[i] | \
                 Mux(gates[i-1], 0, result[intervals[0][1]:])[:end-start]
             print("select: [%d:%d]" % (start, end))
-            res = Signal(width, name="res%d" % i, reset_less=True)
+            res = Signal(reswid, name="res%d" % i, reset_less=True)
             comb += res.eq(result)
             result = res
             s,e = intervals[0]