From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 26 Sep 2019 20:40:38 +0000 (-0700)
Subject: Zero out ports
X-Git-Tag: working-ls180~1039^2~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=58f31096abbb0bc68c8339c88b7db410b8edcdba;p=yosys.git

Zero out ports
---

diff --git a/passes/pmgen/xilinx_dsp_cascade.pmg b/passes/pmgen/xilinx_dsp_cascade.pmg
index 2fc943a66..d4b4b8e22 100644
--- a/passes/pmgen/xilinx_dsp_cascade.pmg
+++ b/passes/pmgen/xilinx_dsp_cascade.pmg
@@ -67,7 +67,7 @@ finally
 					Wire *cascade = module->addWire(NEW_ID, 30);
 					dsp_pcin->setPort(ID(ACIN), cascade);
 					dsp->setPort(ID(ACOUT), cascade);
-					dsp_pcin->unsetPort(ID(A));
+					dsp_pcin->setPort(ID(A), Const(0, 30));
 					add_siguser(cascade, dsp_pcin);
 					add_siguser(cascade, dsp);
 
@@ -80,7 +80,7 @@ finally
 					Wire *cascade = module->addWire(NEW_ID, 18);
 					dsp_pcin->setPort(ID(BCIN), cascade);
 					dsp->setPort(ID(BCOUT), cascade);
-					dsp_pcin->unsetPort(ID(B));
+					dsp_pcin->setPort(ID(B), Const(0, 18));
 					add_siguser(cascade, dsp_pcin);
 					add_siguser(cascade, dsp);