From: Sebastien Bourdeauducq Date: Mon, 6 Feb 2012 22:13:35 +0000 (+0100) Subject: sram: fix sub-word write X-Git-Tag: 24jan2021_ls180~3258 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=58f4f78d2c6337017a0da0a32dc85ab68d6cc84c;p=litex.git sram: fix sub-word write --- diff --git a/milkymist/sram/__init__.py b/milkymist/sram/__init__.py index 792ae152..d30bf87f 100644 --- a/milkymist/sram/__init__.py +++ b/milkymist/sram/__init__.py @@ -9,7 +9,7 @@ class SRAM: def get_fragment(self): # generate write enable signal we = Signal(BV(4)) - comb = [we[i].eq(self.bus.cyc_i & self.bus.stb_i & self.bus.we_i & self.bus.sel_i[3-i]) + comb = [we[i].eq(self.bus.cyc_i & self.bus.stb_i & self.bus.we_i & self.bus.sel_i[i]) for i in range(4)] # split address nbits = bits_for(self.depth-1) diff --git a/top.py b/top.py index 7014158e..8d2bb1f9 100644 --- a/top.py +++ b/top.py @@ -8,7 +8,7 @@ import constraints def get(): MHz = 1000000 clk_freq = 80*MHz - sram_size = 4096 # in kilobytes + sram_size = 4096 # in bytes clkfx_sys = clkfx.ClkFX(50*MHz, clk_freq) reset0 = m1reset.M1Reset()