From: Andreas Krebbel Date: Fri, 24 Mar 2017 13:57:19 +0000 (+0000) Subject: S/390: movdf improvements X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=590961cff2aefdba30048ac5edd228f19114e72c;p=gcc.git S/390: movdf improvements This patch add the vector load element from immediate instruction to the movdf/dd pattern for loading a FP zero and it removes the vector instructions from the mov_64 pattern. These were pointless in there because z13 support implies DFP support so these instructions will always be matched in the mov_64dfp pattern instead. Regression tested on s390x gcc/ChangeLog: 2017-03-24 Andreas Krebbel * config/s390/s390.md ("mov_64dfp" DD_DF): Use vleig for loading a FP zero. ("*mov_64" DD_DF): Remove the vector instructions. These will anyway by matched by mov_64dfp. From-SVN: r246448 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0b76aa4ea6c..bf69f7a4d8d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2017-03-24 Andreas Krebbel + + * config/s390/s390.md ("mov_64dfp" DD_DF): Use vleig for loading a + FP zero. + ("*mov_64" DD_DF): Remove the vector instructions. These + will anyway by matched by mov_64dfp. + 2017-03-24 Andreas Krebbel * config/s390/s390.md ("mov" SD_SF): Change vleg/vsteg to diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 75b15df418b..554fb37a1c6 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -2460,9 +2460,9 @@ (define_insn "*mov_64dfp" [(set (match_operand:DD_DF 0 "nonimmediate_operand" - "=f,f,f,d,f,f,R,T,d,d,d,d,b,T,v,v,d,v,R") + "=f,f,f,d,f,f,R,T,d,d,d,d,b,T,v,v,v,d,v,R") (match_operand:DD_DF 1 "general_operand" - " G,f,d,f,R,T,f,f,G,d,b,T,d,d,v,d,v,R,v"))] + " G,f,d,f,R,T,f,f,G,d,b,T,d,d,v,G,d,v,R,v"))] "TARGET_DFP" "@ lzdr\t%0 @@ -2480,19 +2480,20 @@ stgrl\t%1,%0 stg\t%1,%0 vlr\t%v0,%v1 + vleig\t%v0,0,0 vlvgg\t%v0,%1,0 vlgvg\t%0,%v1,0 vleg\t%0,%1,0 vsteg\t%1,%0,0" - [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRS,VRS,VRX,VRX") + [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRI,VRS,VRS,VRX,VRX") (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, - fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,load,store") - (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*") - (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx,vx,vx")]) + fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,*,load,store") + (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*,*") + (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx,vx,vx,vx")]) (define_insn "*mov_64" - [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T,v,v,R") - (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,T,d,d,v,R,v"))] + [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T") + (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,T,d,d"))] "TARGET_ZARCH" "@ lzdr\t%0 @@ -2506,15 +2507,12 @@ lgrl\t%0,%1 lg\t%0,%1 stgrl\t%1,%0 - stg\t%1,%0 - vlr\t%v0,%v1 - vleg\t%v0,%1,0 - vsteg\t%v1,%0,0" - [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRX,VRX") + stg\t%1,%0" + [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY") (set_attr "type" "fsimpdf,fload,fload,fload, - fstore,fstore,*,lr,load,load,store,store,*,load,store") - (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*") - (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx")]) + fstore,fstore,*,lr,load,load,store,store") + (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") + (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*")]) (define_insn "*mov_31" [(set (match_operand:DD_DF 0 "nonimmediate_operand"