From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 28 Mar 2019 13:51:01 +0000 (+0000)
Subject: reorg, move similar classes to multipipe
X-Git-Tag: ls180-24jan2020~1435
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=590c8216029240bce11dbffbc35d0e02837644b6;p=ieee754fpu.git

reorg, move similar classes to multipipe
---

diff --git a/src/add/multipipe.py b/src/add/multipipe.py
index 2f54c471..0518cfeb 100644
--- a/src/add/multipipe.py
+++ b/src/add/multipipe.py
@@ -267,6 +267,18 @@ class CombMultiInPipeline(MultiInControlBase):
         return m
 
 
+class CombMuxOutPipe(CombMultiOutPipeline):
+    def __init__(self, stage, n_len):
+        # HACK: stage is also the n-way multiplexer
+        CombMultiOutPipeline.__init__(self, stage, n_len=n_len, n_mux=stage)
+
+        # HACK: n-mux is also the stage... so set the muxid equal to input mid
+        stage.m_id = self.p.i_data.mid
+
+    def ports(self):
+        return self.p_mux.ports()
+
+
 class InputPriorityArbiter:
     """ arbitration module for Input-Mux pipe, baed on PriorityEncoder
     """
diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 865783a9..0db44b90 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -10,7 +10,7 @@ from math import log
 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
 from fpbase import MultiShiftRMerge, Trigger
 from singlepipe import (ControlBase, StageChain, UnbufferedPipeline)
-from multipipe import CombMultiOutPipeline
+from multipipe import CombMuxOutPipe
 from multipipe import PriorityCombMuxInPipe
 
 #from fpbase import FPNumShiftMultiRight
@@ -1934,18 +1934,6 @@ class FPADDInMuxPipe(PriorityCombMuxInPipe):
         return res
 
 
-class MuxCombPipeline(CombMultiOutPipeline):
-    def __init__(self, stage, n_len):
-        # HACK: stage is also the n-way multiplexer
-        CombMultiOutPipeline.__init__(self, stage, n_len=n_len, n_mux=stage)
-
-        # HACK: n-mux is also the stage... so set the muxid equal to input mid
-        stage.m_id = self.p.i_data.mid
-
-    def ports(self):
-        return self.p_mux.ports()
-
-
 class FPAddOutPassThruStage:
     def __init__(self, width, id_wid):
         self.width, self.id_wid = width, id_wid
@@ -1954,13 +1942,11 @@ class FPAddOutPassThruStage:
     def process(self, i): return i
 
 
-class FPADDMuxOutPipe(MuxCombPipeline):
+class FPADDMuxOutPipe(CombMuxOutPipe):
     def __init__(self, width, id_wid, num_rows):
         self.num_rows = num_rows
         stage = FPAddOutPassThruStage(width, id_wid)
-        MuxCombPipeline.__init__(self, stage, n_len=self.num_rows)
-        #self.p.i_data = stage.ispec()
-        #self.n.o_data = stage.ospec()
+        CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows)
 
     def ports(self):
         res = [self.p.i_valid, self.p.o_ready] + \
diff --git a/src/add/test_inout_mux_pipe.py b/src/add/test_inout_mux_pipe.py
index c30ba644..ada5e1cb 100644
--- a/src/add/test_inout_mux_pipe.py
+++ b/src/add/test_inout_mux_pipe.py
@@ -11,23 +11,11 @@ from nmigen import Module, Signal, Cat, Value
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
-from multipipe import CombMultiOutPipeline
+from multipipe import CombMultiOutPipeline, CombMuxOutPipe
 from multipipe import PriorityCombMuxInPipe
 from singlepipe import UnbufferedPipeline
 
 
-class MuxCombPipeline(CombMultiOutPipeline):
-    def __init__(self, stage, n_len):
-        # HACK: stage is also the n-way multiplexer
-        CombMultiOutPipeline.__init__(self, stage, n_len=n_len, n_mux=stage)
-
-        # HACK: n-mux is also the stage... so set the muxid equal to input mid
-        stage.m_id = self.p.i_data.mid
-
-    def ports(self):
-        return self.p_mux.ports()
-
-
 class PassData: # (Value):
     def __init__(self):
         self.mid = Signal(2, reset_less=True)
@@ -204,11 +192,11 @@ class OutputTest:
         yield rs.i_valid.eq(0)
 
 
-class TestMuxOutPipe(MuxCombPipeline):
+class TestMuxOutPipe(CombMuxOutPipe):
     def __init__(self, num_rows):
         self.num_rows = num_rows
         stage = PassThroughStage()
-        MuxCombPipeline.__init__(self, stage, n_len=self.num_rows)
+        CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows)
 
     def ports(self):
         res = [self.p.i_valid, self.p.o_ready] + \
diff --git a/src/add/test_outmux_pipe.py b/src/add/test_outmux_pipe.py
index 560ef738..3e8a5559 100644
--- a/src/add/test_outmux_pipe.py
+++ b/src/add/test_outmux_pipe.py
@@ -4,22 +4,10 @@ from nmigen import Module, Signal, Cat
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
-from multipipe import CombMultiOutPipeline
+from multipipe import CombMuxOutPipe
 from singlepipe import UnbufferedPipeline
 
 
-class MuxUnbufferedPipeline(CombMultiOutPipeline):
-    def __init__(self, stage, n_len):
-        # HACK: stage is also the n-way multiplexer
-        CombMultiOutPipeline.__init__(self, stage, n_len=n_len, n_mux=stage)
-
-        # HACK: n-mux is also the stage... so set the muxid equal to input mid
-        stage.m_id = self.p.i_data.mid
-
-    def ports(self):
-        return self.p_mux.ports()
-
-
 class PassInData:
     def __init__(self):
         self.mid = Signal(2, reset_less=True)
@@ -227,11 +215,11 @@ class OutputTest:
                     yield
 
 
-class TestPriorityMuxPipe(MuxUnbufferedPipeline):
+class TestPriorityMuxPipe(CombMuxOutPipe):
     def __init__(self, num_rows):
         self.num_rows = num_rows
         stage = PassThroughStage()
-        MuxUnbufferedPipeline.__init__(self, stage, n_len=self.num_rows)
+        CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows)
 
     def ports(self):
         res = [self.p.i_valid, self.p.o_ready] + \