From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 22 Jun 2022 10:39:36 +0000 (+0100)
Subject: moved sof/sif/sbf to obsolete, redo
X-Git-Tag: opf_rfc_ls005_v1~1604
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=590ca6eb7912cd9ae9d66f773093d586d8fa32b9;p=libreriscv.git

moved sof/sif/sbf to obsolete, redo
---

diff --git a/openpower/sv/vector_ops/discussion.mdwn b/openpower/sv/vector_ops/discussion.mdwn
index 397807cec..3f8765b66 100644
--- a/openpower/sv/vector_ops/discussion.mdwn
+++ b/openpower/sv/vector_ops/discussion.mdwn
@@ -1,5 +1,103 @@
 [[!tag standards]]
 
+# sof/sif/sbfm etc.
+
+These all it turns out can be done as bitmanip of the form
+x/~x &/|/^ (x / -x / x+1 / x-1) so are being superceded.
+needs some work though
+
+## OBSOLETE sbfm
+
+   sbfm RT, RA, RB!=0
+
+Example
+
+     7 6 5 4 3 2 1 0   Bit index
+
+     1 0 0 1 0 1 0 0   v3 contents
+                       vmsbf.m v2, v3
+     0 0 0 0 0 0 1 1   v2 contents
+
+     1 0 0 1 0 1 0 1   v3 contents
+                       vmsbf.m v2, v3
+     0 0 0 0 0 0 0 0   v2
+
+     0 0 0 0 0 0 0 0   v3 contents
+                       vmsbf.m v2, v3
+     1 1 1 1 1 1 1 1   v2
+
+     1 1 0 0 0 0 1 1   RB vcontents
+     1 0 0 1 0 1 0 0   v3 contents
+                       vmsbf.m v2, v3, v0.t
+     0 1 x x x x 1 1   v2 contents
+
+The vmsbf.m instruction takes a mask register as input and writes results to a mask register. The instruction writes a 1 to all active mask elements before the first source element that is a 1, then writes a 0 to that element and all following active elements. If there is no set bit in the source vector, then all active elements in the destination are written with a 1.
+
+Executable pseudocode demo:
+
+```
+[[!inline quick="yes" raw="yes" pages="openpower/sv/sbf.py"]]
+```
+
+## OBSOLETE sifm
+
+The vector mask set-including-first instruction is similar to set-before-first, except it also includes the element with a set bit.
+
+    sifm RT, RA, RB!=0
+
+ # Example
+
+     7 6 5 4 3 2 1 0   Bit number
+
+     1 0 0 1 0 1 0 0   v3 contents
+                       vmsif.m v2, v3
+     0 0 0 0 0 1 1 1   v2 contents
+
+     1 0 0 1 0 1 0 1   v3 contents
+                       vmsif.m v2, v3
+     0 0 0 0 0 0 0 1   v2
+
+     1 1 0 0 0 0 1 1   RB vcontents
+     1 0 0 1 0 1 0 0   v3 contents
+                       vmsif.m v2, v3, v0.t
+     1 1 x x x x 1 1   v2 contents
+
+Executable pseudocode demo:
+
+```
+[[!inline quick="yes" raw="yes" pages="openpower/sv/sif.py"]]
+```
+
+## OBSOLETE vmsof
+
+The vector mask set-only-first instruction is similar to set-before-first, except it only sets the first element with a bit set, if any.
+
+    sofm RT, RA, RB
+
+Example
+
+     7 6 5 4 3 2 1 0   Bit number
+
+     1 0 0 1 0 1 0 0   v3 contents
+                       vmsof.m v2, v3
+     0 0 0 0 0 1 0 0   v2 contents
+
+     1 0 0 1 0 1 0 1   v3 contents
+                       vmsof.m v2, v3
+     0 0 0 0 0 0 0 1   v2
+
+     1 1 0 0 0 0 1 1   RB vcontents
+     1 1 0 1 0 1 0 0   v3 contents
+                       vmsof.m v2, v3, v0.t
+     0 1 x x x x 0 0   v2 content
+
+Executable pseudocode demo:
+
+```
+[[!inline quick="yes" raw="yes" pages="openpower/sv/sof.py"]]
+```
+
+
 # SV Vector Operations not added
 
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