From: Brian Paul <brianp@vmware.com>
Date: Wed, 14 Jan 2009 23:26:41 +0000 (-0700)
Subject: i965: fix some FBO depth/stencil assertions
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5912cdff3e1f2296b1f5753a008b225bdac4559a;p=mesa.git

i965: fix some FBO depth/stencil assertions
---

diff --git a/src/mesa/drivers/dri/intel/intel_depthstencil.c b/src/mesa/drivers/dri/intel/intel_depthstencil.c
index c2b4d7728b4..f43b9aed486 100644
--- a/src/mesa/drivers/dri/intel/intel_depthstencil.c
+++ b/src/mesa/drivers/dri/intel/intel_depthstencil.c
@@ -177,8 +177,11 @@ intel_validate_paired_depth_stencil(GLcontext * ctx,
       }
       else {
          /* Separate depth/stencil buffers, need to interleave now */
-         ASSERT(depthRb->Base._BaseFormat == GL_DEPTH_COMPONENT);
-         ASSERT(stencilRb->Base._BaseFormat == GL_STENCIL_INDEX);
+         ASSERT(depthRb->Base._BaseFormat == GL_DEPTH_COMPONENT ||
+                depthRb->Base._BaseFormat == GL_DEPTH_STENCIL);
+         ASSERT(stencilRb->Base._BaseFormat == GL_STENCIL_INDEX ||
+                stencilRb->Base._BaseFormat == GL_DEPTH_STENCIL);
+
          /* may need to interleave depth/stencil now */
          if (depthRb->PairedStencil == stencilRb->Base.Name) {
             /* OK, the depth and stencil buffers are already interleaved */