From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 4 May 2021 12:31:35 +0000 (+0100)
Subject: add option to add exception type to FUBaseData (pipe_data)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5919b89de8a6f1bb7fce42c8cacd9dd38f126901;p=soc.git

add option to add exception type to FUBaseData (pipe_data)
---

diff --git a/src/soc/fu/pipe_data.py b/src/soc/fu/pipe_data.py
index 1f780336..ca67fd1b 100644
--- a/src/soc/fu/pipe_data.py
+++ b/src/soc/fu/pipe_data.py
@@ -16,11 +16,13 @@ class FUBaseData:
     pipeline *to* output) must have it set to "True".
     """
 
-    def __init__(self, pspec, output):
+    def __init__(self, pspec, output, exc_kls=None):
         self.ctx = PipeContext(pspec) # context for ReservationStation usage
         self.muxid = self.ctx.muxid
         self.data = []
         self.is_output = output
+        # take regspec and create data attributes (in or out)
+        # TODO: use widspec to create reduced bit mapping.
         for i, (regfile, regname, widspec) in enumerate(self.regspec):
             wid = get_regspec_bitwidth([self.regspec], 0, i)
             if output:
@@ -29,6 +31,11 @@ class FUBaseData:
                 sig = Signal(wid, name=regname, reset_less=True)
             setattr(self, regname, sig)
             self.data.append(sig)
+        # optional exception type
+        if exc_kls is not None:
+            name = "exc_o" if output else "exc_i"
+            self.exception = exc_kls(name=name)
+            self.data.append(self.exception)
 
     def __iter__(self):
         yield from self.ctx