From: Luke Kenneth Casson Leighton Date: Sun, 25 Aug 2019 10:04:02 +0000 (+0100) Subject: remove out_do_z from add0 X-Git-Tag: ls180-24jan2020~388 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5922c8304ac8abce20d2f2297f28899f9d98f4cb;p=ieee754fpu.git remove out_do_z from add0 --- diff --git a/src/ieee754/fpadd/add0.py b/src/ieee754/fpadd/add0.py index 2110f81b..a88dc061 100644 --- a/src/ieee754/fpadd/add0.py +++ b/src/ieee754/fpadd/add0.py @@ -35,30 +35,29 @@ class FPAddStage0Mod(PipeModBase): am0 = Signal(len(self.i.a.m)+1, reset_less=True) bm0 = Signal(len(self.i.b.m)+1, reset_less=True) # same-sign (both negative or both positive) add mantissas - with m.If(~self.i.out_do_z): - comb += [seq.eq(self.i.a.s == self.i.b.s), - mge.eq(self.i.a.m >= self.i.b.m), - am0.eq(Cat(self.i.a.m, 0)), - bm0.eq(Cat(self.i.b.m, 0)) - ] - comb += self.o.z.e.eq(self.i.a.e) - with m.If(seq): - comb += [ - self.o.tot.eq(am0 + bm0), - self.o.z.s.eq(self.i.a.s) + comb += [seq.eq(self.i.a.s == self.i.b.s), + mge.eq(self.i.a.m >= self.i.b.m), + am0.eq(Cat(self.i.a.m, 0)), + bm0.eq(Cat(self.i.b.m, 0)) ] - # a mantissa greater than b, use a - with m.Elif(mge): - comb += [ - self.o.tot.eq(am0 - bm0), - self.o.z.s.eq(self.i.a.s) - ] - # b mantissa greater than a, use b - with m.Else(): - comb += [ - self.o.tot.eq(bm0 - am0), - self.o.z.s.eq(self.i.b.s) + comb += self.o.z.e.eq(self.i.a.e) + with m.If(seq): + comb += [ + self.o.tot.eq(am0 + bm0), + self.o.z.s.eq(self.i.a.s) + ] + # a mantissa greater than b, use a + with m.Elif(mge): + comb += [ + self.o.tot.eq(am0 - bm0), + self.o.z.s.eq(self.i.a.s) ] + # b mantissa greater than a, use b + with m.Else(): + comb += [ + self.o.tot.eq(bm0 - am0), + self.o.z.s.eq(self.i.b.s) + ] # pass-through context comb += self.o.oz.eq(self.i.oz)