From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 10 Apr 2023 10:22:38 +0000 (+0100)
Subject: whoops heading1 not heading2
X-Git-Tag: opf_rfc_ls012_v1~33
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=592a3e40379710bae41ccd3cb4ac96cabbeeb467;p=libreriscv.git

whoops heading1 not heading2
---

diff --git a/openpower/sv/rfc/ls012.mdwn b/openpower/sv/rfc/ls012.mdwn
index 77df72492..475d4b3b2 100644
--- a/openpower/sv/rfc/ls012.mdwn
+++ b/openpower/sv/rfc/ls012.mdwn
@@ -316,7 +316,7 @@ introduce mv Swizzle operations, which can always be Macro-op fused
 in exactly the same way that ARM SVE predicated-move extends 3-operand
 "overwrite" opcodes to full independent 3-in 1-out.
 
-# BMI (bitmanipulation) group.
+## BMI (bitmanipulation) group.
 
 Whilst the [[sv/vector_ops]] instructions are only two in number, in
 reality the `bmask` instruction has a Mode field allowing it to cover