From: Eddie Hung Date: Thu, 23 Apr 2020 00:43:25 +0000 (-0700) Subject: xilinx: xilinx_dsp_cascade to check CREG for DSP48E1 only X-Git-Tag: working-ls180~594^2~2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=592baebd22ab1c80512b6f91926d90b33393285e;p=yosys.git xilinx: xilinx_dsp_cascade to check CREG for DSP48E1 only --- diff --git a/passes/pmgen/xilinx_dsp_cascade.pmg b/passes/pmgen/xilinx_dsp_cascade.pmg index a36edd9e5..8babb88e6 100644 --- a/passes/pmgen/xilinx_dsp_cascade.pmg +++ b/passes/pmgen/xilinx_dsp_cascade.pmg @@ -188,7 +188,7 @@ arg next // driven by the 'P' output of the previous DSP cell, and (c) has its // 'PCIN' port unused match nextP - select !param(nextP, \CREG).as_bool() + select !nextP->type.in(\DSP48E1) || !param(nextP, \CREG).as_bool() select (nextP->type.in(\DSP48A, \DSP48A1) && port(nextP, \OPMODE, Const(0, 8)).extract(2,2) == Const::from_string("11")) || (nextP->type.in(\DSP48E1) && port(nextP, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("011")) select nusers(port(nextP, \C, SigSpec())) > 1 select nusers(port(nextP, \PCIN, SigSpec())) == 0