From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 12 Aug 2014 13:21:06 +0000 (+0200)
Subject: Fixed building verific bindings
X-Git-Tag: yosys-0.4~280
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=593264e9edce8b1df1d5b691353fa592261d4f3b;p=yosys.git

Fixed building verific bindings
---

diff --git a/frontends/verific/build_amd64.txt b/frontends/verific/build_amd64.txt
index 2f325e515..2c3ba7b4d 100644
--- a/frontends/verific/build_amd64.txt
+++ b/frontends/verific/build_amd64.txt
@@ -6,7 +6,7 @@ only have the i386 eval version of Verific:
 1.) Use a Makefile.conf like the following one:
 
 --snip--
-CONFIG := clang-debug
+CONFIG := clang
 ENABLE_TCL := 0
 ENABLE_QT4 := 0
 ENABLE_ABC := 0
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 30f452181..1ffcc4229 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -687,7 +687,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
 			RTLIL::SigSpec data = operatorOutput(inst, net_map, module);
 
 			RTLIL::Cell *cell = module->addCell(RTLIL::escape_id(inst->Name()), "$memrd");
-			cell->parameters["\\MEMID"] = memory->name;
+			cell->parameters["\\MEMID"] = memory->name.str();
 			cell->parameters["\\CLK_ENABLE"] = false;
 			cell->parameters["\\CLK_POLARITY"] = true;
 			cell->parameters["\\TRANSPARENT"] = false;
@@ -709,7 +709,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
 			RTLIL::SigSpec data = operatorInput2(inst, net_map);
 
 			RTLIL::Cell *cell = module->addCell(RTLIL::escape_id(inst->Name()), "$memwr");
-			cell->parameters["\\MEMID"] = memory->name;
+			cell->parameters["\\MEMID"] = memory->name.str();
 			cell->parameters["\\CLK_ENABLE"] = false;
 			cell->parameters["\\CLK_POLARITY"] = true;
 			cell->parameters["\\PRIORITY"] = 0;