From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Jul 2019 22:50:13 +0000 (-0700)
Subject: Do not do sign extension in techmap; let packer do it
X-Git-Tag: working-ls180~1039^2~315
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=595a8f032f1e9db385959f92a4a414a40de291fd;p=yosys.git

Do not do sign extension in techmap; let packer do it
---

diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
index 5444d842a..70c2c42c6 100644
--- a/techlibs/common/mul2dsp.v
+++ b/techlibs/common/mul2dsp.v
@@ -196,24 +196,15 @@ module \$__mul (A, B, Y);
 			assign Y = partial_sum[n-1];
 		end
 		else begin 
-			if (A_SIGNED)
-				wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A);
-			else
-				wire [`DSP_A_MAXWIDTH-1:0] Aext = A;
-			if (B_SIGNED)
-				wire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B);
-			else
-				wire [`DSP_B_MAXWIDTH-1:0] Bext = B;
-
 			`DSP_NAME #(
 				.A_SIGNED(A_SIGNED),
 				.B_SIGNED(B_SIGNED),
-				.A_WIDTH(`DSP_A_MAXWIDTH),
-				.B_WIDTH(`DSP_B_MAXWIDTH),
-				.Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)),
+				.A_WIDTH(A_WIDTH),
+				.B_WIDTH(B_WIDTH),
+				.Y_WIDTH(`MIN(Y_WIDTH,A_WIDTH+B_WIDTH)),
 			) _TECHMAP_REPLACE_ (
-				.A(Aext),
-				.B(Bext),
+				.A(A),
+				.B(B),
 				.Y(Y)
 			);
 		end