From: Jeffrey A Law <law@cygnus.com>
Date: Sat, 30 Jan 1999 13:50:10 +0000 (+0000)
Subject: pa.md (parallel shift and shiftadd): Mark output of shift as an earlyclobber.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5989c468fb8579b16e0bbb2b4528a832cabc5931;p=gcc.git

pa.md (parallel shift and shiftadd): Mark output of shift as an earlyclobber.

        * pa.md (parallel shift and shiftadd): Mark output of shift as an
        earlyclobber.
Fixes -O1 bootstrap problem.

From-SVN: r24922
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 04ddeb0c141..1aa52ffb0a3 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,8 @@
 Sat Jan 30 08:27:23 1999  Jeffrey A Law  (law@cygnus.com)
 
+	* pa.md (parallel shift and shiftadd): Mark output of shift as an
+	earlyclobber.
+
 	* loop.c: Disable recent loop changes.  Temporary as Joern
 	continues to fix problems.
 
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index ada7553d99f..5775e201624 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -3627,6 +3627,28 @@
   [(set_attr "type" "binary")
    (set_attr "length" "4")])
 
+;; This variant of the above insn can occur if the first operand
+;; is the frame pointer.  This is a kludge, but there doesn't
+;; seem to be a way around it.  Only recognize it while reloading.
+;; Note how operand 3 uses a predicate of "const_int_operand", but 
+;; has constraints allowing a register.  I don't know how this works,
+;; but it somehow makes sure that out-of-range constants are placed
+;; in a register which somehow magically is a "const_int_operand".
+;; (this was stolen from alpha.md, I'm not going to try and change it.
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=&r,r")
+	(plus:SI (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r,r")
+				   (match_operand:SI 4 "shadd_operand" ""))
+			  (match_operand:SI 1 "register_operand" "r,r"))
+		 (match_operand:SI 3 "const_int_operand" "r,J")))]
+  "reload_in_progress"
+  "@
+   sh%O4addl %2,%1,%0\;addl %3,%0,%0
+   sh%O4addl %2,%1,%0\;ldo %3(%0),%0"
+  [(set_attr "type" "multi")
+   (set_attr "length" "8")])
+
 ;; This anonymous pattern and splitter wins because it reduces the latency
 ;; of the shadd sequence without increasing the latency of the shift.
 ;;
@@ -3636,12 +3658,15 @@
 ;; It would be clearer if combine used the same operator for both expressions,
 ;; it's somewhat confusing to have a mult in ine operation and an ashift
 ;; in the other.
+;;
+;; If this pattern is not split before register allocation, then we must expose
+;; the fact that operand 4 is set before operands 1, 2 and 3 have been read.
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
 			  (match_operand:SI 3 "shadd_operand" ""))
 		 (match_operand:SI 1 "register_operand" "r")))
-   (set (match_operand:SI 4 "register_operand" "=r")
+   (set (match_operand:SI 4 "register_operand" "=&r")
 	(ashift:SI (match_dup 2)
 		   (match_operand:SI 5 "const_int_operand" "i")))]
   "INTVAL (operands[5]) == exact_log2 (INTVAL (operands[3]))"
@@ -3654,7 +3679,7 @@
 	(plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
 			  (match_operand:SI 3 "shadd_operand" ""))
 		 (match_operand:SI 1 "register_operand" "r")))
-   (set (match_operand:SI 4 "register_operand" "=r")
+   (set (match_operand:SI 4 "register_operand" "=&r")
 	(ashift:SI (match_dup 2)
 		   (match_operand:SI 5 "const_int_operand" "i")))]
   "INTVAL (operands[5]) == exact_log2 (INTVAL (operands[3]))"
@@ -3663,28 +3688,6 @@
 			       (match_dup 1)))]
   "")
 
-;; This variant of the above insn can occur if the first operand
-;; is the frame pointer.  This is a kludge, but there doesn't
-;; seem to be a way around it.  Only recognize it while reloading.
-;; Note how operand 3 uses a predicate of "const_int_operand", but 
-;; has constraints allowing a register.  I don't know how this works,
-;; but it somehow makes sure that out-of-range constants are placed
-;; in a register which somehow magically is a "const_int_operand".
-;; (this was stolen from alpha.md, I'm not going to try and change it.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r,r")
-	(plus:SI (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r,r")
-				   (match_operand:SI 4 "shadd_operand" ""))
-			  (match_operand:SI 1 "register_operand" "r,r"))
-		 (match_operand:SI 3 "const_int_operand" "r,J")))]
-  "reload_in_progress"
-  "@
-   sh%O4addl %2,%1,%0\;addl %3,%0,%0
-   sh%O4addl %2,%1,%0\;ldo %3(%0),%0"
-  [(set_attr "type" "multi")
-   (set_attr "length" "8")])
-
 (define_expand "ashlsi3"
   [(set (match_operand:SI 0 "register_operand" "")
 	(ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")