From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 5 Nov 2021 09:04:15 +0000 (+0100)
Subject: Update command reference
X-Git-Tag: yosys-0.11~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=598f51c6a1e4542e40eaf82490e171d23d0265fc;p=yosys.git

Update command reference
---

diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex
index b3ab02b97..ccfae8bff 100644
--- a/manual/command-reference-manual.tex
+++ b/manual/command-reference-manual.tex
@@ -3654,6 +3654,11 @@ Additional -D<macro>[=<value>] options may be added after the option indicating
 the language version (and before file names) to set additional verilog defines.
 
 
+    read {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..
+
+Load the specified VHDL files. (Requires Verific.)
+
+
     read {-f|-F} <command-file>
 
 Load and execute the specified command file. (Requires Verific.)
@@ -7316,6 +7321,11 @@ The macros SYNTHESIS and VERIFIC are defined implicitly.
 Like -sv, but define FORMAL instead of SYNTHESIS.
 
 
+    verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..
+
+Load the specified VHDL files into Verific.
+
+
     verific {-f|-F} <command-file>
 
 Load and execute the specified command file.
@@ -7502,6 +7512,13 @@ Templates:
 
   WARNING: Templates only available in commercial build.
 
+
+
+    verific -cfg [<name> [<value>]]
+
+Get/set Verific runtime flags.
+
+
 Use YosysHQ Tabby CAD Suite if you need Yosys+Verific.
 https://www.yosyshq.com/