From: programmerjake Date: Thu, 22 Dec 2022 22:48:21 +0000 (+0000) Subject: use OpenPower naming where appropriate and add fp8 link X-Git-Tag: opf_rfc_ls005_v1~2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5997033c3e258bc2c5c48f147abb1c4a10c2a21f;p=libreriscv.git use OpenPower naming where appropriate and add fp8 link --- diff --git a/openpower/sv/rfc/ls005.mdwn b/openpower/sv/rfc/ls005.mdwn index f5100cd4c..2e05d4f8b 100644 --- a/openpower/sv/rfc/ls005.mdwn +++ b/openpower/sv/rfc/ls005.mdwn @@ -103,12 +103,11 @@ the full width". "half width" exactly as presently defined. * XLEN=32 overrides FPR "full width" operations to full BFP32, and "half width" to be "BFP16 stored in an BFP32" -* XLEN=16 redefines FPR "full width" operations to full [IEEE FP16](https://en.wikipedia.org/wiki/Half-precision_floating-point_format) and leaves - "half width" UNDEFINED (there is no IEEE FP8). -* XLEN=8 redefines FPR "full width" operations to [BF16 (bfloat16)](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format) and leaves +* XLEN=16 redefines FPR "full width" operations to full [IEEE BFP16](https://en.wikipedia.org/wiki/Half-precision_floating-point_format) and leaves + "half width" UNDEFINED (there is no IEEE version of [FP8](https://wccftech.com/nvidia-intel-arm-bet-their-ai-future-on-fp8-whitepaper-for-8-bit-fp-published/)). +* XLEN=8 redefines FPR "full width" operations to [bfloat16](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format) and leaves "half width" UNDEFINED. ---------------- \newpage{} -