From: Michael Nolan <mtnolan2640@gmail.com>
Date: Fri, 22 May 2020 14:49:26 +0000 (-0400)
Subject: Convert branch unit to new CR interface
X-Git-Tag: div_pipeline~944
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5998d1bce10e6ed9ce0d8b9614801cca9fd21c35;p=soc.git

Convert branch unit to new CR interface
---

diff --git a/src/soc/fu/branch/main_stage.py b/src/soc/fu/branch/main_stage.py
index 723182f4..636e581c 100644
--- a/src/soc/fu/branch/main_stage.py
+++ b/src/soc/fu/branch/main_stage.py
@@ -75,11 +75,13 @@ class BranchMainStage(PipeModBase):
         # https://bugs.libre-soc.org/show_bug.cgi?id=313#c2
         b_fields = self.fields.FormB
         BO = b_fields.BO[0:-1]
-        BI = b_fields.BI[0:-1]
+        BI = b_fields.BI[0:-1][0:2]
+
+        cr_bits = Array([cr[3-i] for i in range(4)])
 
         # The bit of CR selected by BI
         cr_bit = Signal(reset_less=True)
-        comb += cr_bit.eq((cr & (1<<(31-BI))) != 0)
+        comb += cr_bit.eq(cr_bits[BI])
 
         # Whether the conditional branch should be taken
         bc_taken = Signal(reset_less=True)
diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py
index 1f79a704..28099eaa 100644
--- a/src/soc/fu/branch/pipe_data.py
+++ b/src/soc/fu/branch/pipe_data.py
@@ -33,7 +33,7 @@ from soc.fu.branch.br_input_record import CompBROpSubset # TODO: replace
 class BranchInputData(IntegerData):
     regspec = [('SPR', 'spr1', '0:63'),
                ('SPR', 'spr2', '0:63'),
-               ('CR', 'cr', '32'),
+               ('CR', 'cr', '4'),
                ('PC', 'cia', '0:63')]
     def __init__(self, pspec):
         super().__init__(pspec)
@@ -43,7 +43,7 @@ class BranchInputData(IntegerData):
 
         self.spr1 = Signal(64, reset_less=True) # see table above, SPR1
         self.spr2 = Signal(64, reset_less=True) # see table above, SPR2
-        self.cr = Signal(32, reset_less=True)   # Condition Register(s) CR0-7
+        self.cr = Signal(4, reset_less=True)   # Condition Register(s) CR0-7
         self.cia = Signal(64, reset_less=True)  # Current Instruction Address
 
         # convenience variables.  not all of these are used at once
diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index 09ccb3fd..541b56dd 100644
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -151,7 +151,6 @@ class TestRunner(FHDLTestCase):
                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
                     yield instruction.eq(ins)          # raw binary instr.
                     yield branch.p.data_i.cia.eq(simulator.pc.CIA.value)
-                    yield branch.p.data_i.cr.eq(simulator.cr.get_range().value)
                     # note, here, the op will need further decoding in order
                     # to set the correct SPRs on SPR1/2/3.  op_bc* require
                     # spr2 to be set to CTR, op_bctar require spr1 to be
@@ -161,6 +160,14 @@ class TestRunner(FHDLTestCase):
                     yield branch.p.data_i.spr2.eq(simulator.spr['CTR'].value)
                     print(f"cr0: {simulator.crl[0].get_range()}")
                     yield Settle()
+
+                    cr_en = yield pdecode2.e.read_cr1.ok
+                    if cr_en:
+                        cr_sel = yield pdecode2.e.read_cr1.data
+                        cr = simulator.crl[cr_sel].get_range().value
+                        yield branch.p.data_i.cr.eq(cr)
+                        full_cr = simulator.cr.get_range().value
+                        print(f"full cr: {full_cr:x}, sel: {cr_sel}, cr: {cr:x}")
                     fn_unit = yield pdecode2.e.fn_unit
                     self.assertEqual(fn_unit, Function.BRANCH.value, code)
                     yield