From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Fri, 5 Jun 2020 01:15:35 +0000 (+1000)
Subject: litedram: Remove old "VexRiscV" based initializations
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=599fad117bef2805a08f7ee8b8fbd92cfc0ceb2c;p=microwatt.git

litedram: Remove old "VexRiscV" based initializations

Support for this has bitrotted and would require refactoring of L2 to
be brought back. It's also not really needed anymore now that we ship
pre-generated litedram and that LiteX supports what we do.

So take it out, which simplifies some of the scripts as well. This also
fixes up CSR alignment the sim model.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---

diff --git a/Makefile b/Makefile
index 298c7da..23c79b2 100644
--- a/Makefile
+++ b/Makefile
@@ -95,7 +95,7 @@ SIM_DRAM_CFLAGS += -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVL_PRINTF=printf -fa
 sim_litedram_c.o: litedram/extras/sim_litedram_c.cpp verilated_dram
 	$(CC)  $(CPPFLAGS) $(SIM_DRAM_CFLAGS) $(CFLAGS) -c $< -o $@
 
-soc_dram_files = $(soc_files) litedram/extras/wrapper-mw-init.vhdl litedram/generated/sim/litedram-initmem.vhdl
+soc_dram_files = $(soc_files) litedram/extras/litedram-wrapper-l2.vhdl litedram/generated/sim/litedram-initmem.vhdl
 soc_dram_sim_files = $(soc_sim_files) litedram/extras/sim_litedram.vhdl
 soc_dram_sim_obj_files = $(soc_sim_obj_files) sim_litedram_c.o
 dram_link_files=-Wl,obj_dir/Vlitedram_core__ALL.a -Wl,obj_dir/verilated.o -Wl,obj_dir/verilated_vcd_c.o -Wl,-lstdc++
diff --git a/litedram/extras/VexRiscv.v b/litedram/extras/VexRiscv.v
deleted file mode 100644
index 0fda9d8..0000000
--- a/litedram/extras/VexRiscv.v
+++ /dev/null
@@ -1,3967 +0,0 @@
-// Generator : SpinalHDL v1.3.6    git head : 9bf01e7f360e003fac1dd5ca8b8f4bffec0e52b8
-// Date      : 23/03/2020, 17:06:53
-// Component : VexRiscv
-
-
-`define Src2CtrlEnum_defaultEncoding_type [1:0]
-`define Src2CtrlEnum_defaultEncoding_RS 2'b00
-`define Src2CtrlEnum_defaultEncoding_IMI 2'b01
-`define Src2CtrlEnum_defaultEncoding_IMS 2'b10
-`define Src2CtrlEnum_defaultEncoding_PC 2'b11
-
-`define EnvCtrlEnum_defaultEncoding_type [1:0]
-`define EnvCtrlEnum_defaultEncoding_NONE 2'b00
-`define EnvCtrlEnum_defaultEncoding_XRET 2'b01
-`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10
-
-`define Src1CtrlEnum_defaultEncoding_type [1:0]
-`define Src1CtrlEnum_defaultEncoding_RS 2'b00
-`define Src1CtrlEnum_defaultEncoding_IMU 2'b01
-`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10
-`define Src1CtrlEnum_defaultEncoding_URS1 2'b11
-
-`define BranchCtrlEnum_defaultEncoding_type [1:0]
-`define BranchCtrlEnum_defaultEncoding_INC 2'b00
-`define BranchCtrlEnum_defaultEncoding_B 2'b01
-`define BranchCtrlEnum_defaultEncoding_JAL 2'b10
-`define BranchCtrlEnum_defaultEncoding_JALR 2'b11
-
-`define AluCtrlEnum_defaultEncoding_type [1:0]
-`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00
-`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01
-`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10
-
-`define ShiftCtrlEnum_defaultEncoding_type [1:0]
-`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00
-`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01
-`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10
-`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11
-
-`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0]
-`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00
-`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01
-`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10
-
-module StreamFifoLowLatency (
-      input   io_push_valid,
-      output  io_push_ready,
-      input   io_push_payload_error,
-      input  [31:0] io_push_payload_inst,
-      output reg  io_pop_valid,
-      input   io_pop_ready,
-      output reg  io_pop_payload_error,
-      output reg [31:0] io_pop_payload_inst,
-      input   io_flush,
-      output [0:0] io_occupancy,
-      input   clk,
-      input   reset);
-  wire  _zz_5_;
-  wire [0:0] _zz_6_;
-  reg  _zz_1_;
-  reg  pushPtr_willIncrement;
-  reg  pushPtr_willClear;
-  wire  pushPtr_willOverflowIfInc;
-  wire  pushPtr_willOverflow;
-  reg  popPtr_willIncrement;
-  reg  popPtr_willClear;
-  wire  popPtr_willOverflowIfInc;
-  wire  popPtr_willOverflow;
-  wire  ptrMatch;
-  reg  risingOccupancy;
-  wire  empty;
-  wire  full;
-  wire  pushing;
-  wire  popping;
-  wire [32:0] _zz_2_;
-  wire [32:0] _zz_3_;
-  reg [32:0] _zz_4_;
-  assign _zz_5_ = (! empty);
-  assign _zz_6_ = _zz_2_[0 : 0];
-  always @ (*) begin
-    _zz_1_ = 1'b0;
-    if(pushing)begin
-      _zz_1_ = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    pushPtr_willIncrement = 1'b0;
-    if(pushing)begin
-      pushPtr_willIncrement = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    pushPtr_willClear = 1'b0;
-    if(io_flush)begin
-      pushPtr_willClear = 1'b1;
-    end
-  end
-
-  assign pushPtr_willOverflowIfInc = 1'b1;
-  assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement);
-  always @ (*) begin
-    popPtr_willIncrement = 1'b0;
-    if(popping)begin
-      popPtr_willIncrement = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    popPtr_willClear = 1'b0;
-    if(io_flush)begin
-      popPtr_willClear = 1'b1;
-    end
-  end
-
-  assign popPtr_willOverflowIfInc = 1'b1;
-  assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement);
-  assign ptrMatch = 1'b1;
-  assign empty = (ptrMatch && (! risingOccupancy));
-  assign full = (ptrMatch && risingOccupancy);
-  assign pushing = (io_push_valid && io_push_ready);
-  assign popping = (io_pop_valid && io_pop_ready);
-  assign io_push_ready = (! full);
-  always @ (*) begin
-    if(_zz_5_)begin
-      io_pop_valid = 1'b1;
-    end else begin
-      io_pop_valid = io_push_valid;
-    end
-  end
-
-  assign _zz_2_ = _zz_3_;
-  always @ (*) begin
-    if(_zz_5_)begin
-      io_pop_payload_error = _zz_6_[0];
-    end else begin
-      io_pop_payload_error = io_push_payload_error;
-    end
-  end
-
-  always @ (*) begin
-    if(_zz_5_)begin
-      io_pop_payload_inst = _zz_2_[32 : 1];
-    end else begin
-      io_pop_payload_inst = io_push_payload_inst;
-    end
-  end
-
-  assign io_occupancy = (risingOccupancy && ptrMatch);
-  assign _zz_3_ = _zz_4_;
-  always @ (posedge clk) begin
-    if(reset) begin
-      risingOccupancy <= 1'b0;
-    end else begin
-      if((pushing != popping))begin
-        risingOccupancy <= pushing;
-      end
-      if(io_flush)begin
-        risingOccupancy <= 1'b0;
-      end
-    end
-  end
-
-  always @ (posedge clk) begin
-    if(_zz_1_)begin
-      _zz_4_ <= {io_push_payload_inst,io_push_payload_error};
-    end
-  end
-
-endmodule
-
-module VexRiscv (
-      input  [31:0] externalResetVector,
-      input   timerInterrupt,
-      input   softwareInterrupt,
-      input  [31:0] externalInterruptArray,
-      output  iBusWishbone_CYC,
-      output  iBusWishbone_STB,
-      input   iBusWishbone_ACK,
-      output  iBusWishbone_WE,
-      output [29:0] iBusWishbone_ADR,
-      input  [31:0] iBusWishbone_DAT_MISO,
-      output [31:0] iBusWishbone_DAT_MOSI,
-      output [3:0] iBusWishbone_SEL,
-      input   iBusWishbone_ERR,
-      output [1:0] iBusWishbone_BTE,
-      output [2:0] iBusWishbone_CTI,
-      output  dBusWishbone_CYC,
-      output  dBusWishbone_STB,
-      input   dBusWishbone_ACK,
-      output  dBusWishbone_WE,
-      output [29:0] dBusWishbone_ADR,
-      input  [31:0] dBusWishbone_DAT_MISO,
-      output [31:0] dBusWishbone_DAT_MOSI,
-      output reg [3:0] dBusWishbone_SEL,
-      input   dBusWishbone_ERR,
-      output [1:0] dBusWishbone_BTE,
-      output [2:0] dBusWishbone_CTI,
-      input   clk,
-      input   reset);
-  reg [31:0] _zz_161_;
-  reg [31:0] _zz_162_;
-  reg [31:0] _zz_163_;
-  wire  IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready;
-  wire  IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid;
-  wire  IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error;
-  wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst;
-  wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy;
-  wire  _zz_164_;
-  wire  _zz_165_;
-  wire  _zz_166_;
-  wire  _zz_167_;
-  wire  _zz_168_;
-  wire  _zz_169_;
-  wire  _zz_170_;
-  wire [1:0] _zz_171_;
-  wire  _zz_172_;
-  wire  _zz_173_;
-  wire  _zz_174_;
-  wire  _zz_175_;
-  wire  _zz_176_;
-  wire  _zz_177_;
-  wire  _zz_178_;
-  wire  _zz_179_;
-  wire  _zz_180_;
-  wire  _zz_181_;
-  wire  _zz_182_;
-  wire  _zz_183_;
-  wire  _zz_184_;
-  wire  _zz_185_;
-  wire  _zz_186_;
-  wire  _zz_187_;
-  wire [1:0] _zz_188_;
-  wire  _zz_189_;
-  wire [3:0] _zz_190_;
-  wire [2:0] _zz_191_;
-  wire [31:0] _zz_192_;
-  wire [2:0] _zz_193_;
-  wire [0:0] _zz_194_;
-  wire [2:0] _zz_195_;
-  wire [0:0] _zz_196_;
-  wire [2:0] _zz_197_;
-  wire [0:0] _zz_198_;
-  wire [2:0] _zz_199_;
-  wire [0:0] _zz_200_;
-  wire [2:0] _zz_201_;
-  wire [2:0] _zz_202_;
-  wire [0:0] _zz_203_;
-  wire [0:0] _zz_204_;
-  wire [0:0] _zz_205_;
-  wire [0:0] _zz_206_;
-  wire [0:0] _zz_207_;
-  wire [0:0] _zz_208_;
-  wire [0:0] _zz_209_;
-  wire [0:0] _zz_210_;
-  wire [0:0] _zz_211_;
-  wire [0:0] _zz_212_;
-  wire [0:0] _zz_213_;
-  wire [0:0] _zz_214_;
-  wire [2:0] _zz_215_;
-  wire [4:0] _zz_216_;
-  wire [11:0] _zz_217_;
-  wire [11:0] _zz_218_;
-  wire [31:0] _zz_219_;
-  wire [31:0] _zz_220_;
-  wire [31:0] _zz_221_;
-  wire [31:0] _zz_222_;
-  wire [31:0] _zz_223_;
-  wire [31:0] _zz_224_;
-  wire [31:0] _zz_225_;
-  wire [31:0] _zz_226_;
-  wire [32:0] _zz_227_;
-  wire [19:0] _zz_228_;
-  wire [11:0] _zz_229_;
-  wire [11:0] _zz_230_;
-  wire [1:0] _zz_231_;
-  wire [1:0] _zz_232_;
-  wire [1:0] _zz_233_;
-  wire [1:0] _zz_234_;
-  wire [0:0] _zz_235_;
-  wire [0:0] _zz_236_;
-  wire [0:0] _zz_237_;
-  wire [0:0] _zz_238_;
-  wire [0:0] _zz_239_;
-  wire [0:0] _zz_240_;
-  wire [6:0] _zz_241_;
-  wire  _zz_242_;
-  wire  _zz_243_;
-  wire [1:0] _zz_244_;
-  wire [31:0] _zz_245_;
-  wire [31:0] _zz_246_;
-  wire [31:0] _zz_247_;
-  wire  _zz_248_;
-  wire [0:0] _zz_249_;
-  wire [0:0] _zz_250_;
-  wire  _zz_251_;
-  wire [0:0] _zz_252_;
-  wire [18:0] _zz_253_;
-  wire [31:0] _zz_254_;
-  wire [31:0] _zz_255_;
-  wire [31:0] _zz_256_;
-  wire [31:0] _zz_257_;
-  wire [31:0] _zz_258_;
-  wire [31:0] _zz_259_;
-  wire  _zz_260_;
-  wire [1:0] _zz_261_;
-  wire [1:0] _zz_262_;
-  wire  _zz_263_;
-  wire [0:0] _zz_264_;
-  wire [14:0] _zz_265_;
-  wire [31:0] _zz_266_;
-  wire [31:0] _zz_267_;
-  wire [31:0] _zz_268_;
-  wire [31:0] _zz_269_;
-  wire [0:0] _zz_270_;
-  wire [0:0] _zz_271_;
-  wire [0:0] _zz_272_;
-  wire [0:0] _zz_273_;
-  wire  _zz_274_;
-  wire [0:0] _zz_275_;
-  wire [11:0] _zz_276_;
-  wire [31:0] _zz_277_;
-  wire [31:0] _zz_278_;
-  wire [31:0] _zz_279_;
-  wire  _zz_280_;
-  wire [0:0] _zz_281_;
-  wire [1:0] _zz_282_;
-  wire [0:0] _zz_283_;
-  wire [0:0] _zz_284_;
-  wire [1:0] _zz_285_;
-  wire [1:0] _zz_286_;
-  wire  _zz_287_;
-  wire [0:0] _zz_288_;
-  wire [8:0] _zz_289_;
-  wire [31:0] _zz_290_;
-  wire [31:0] _zz_291_;
-  wire [31:0] _zz_292_;
-  wire [31:0] _zz_293_;
-  wire [31:0] _zz_294_;
-  wire [31:0] _zz_295_;
-  wire [31:0] _zz_296_;
-  wire [31:0] _zz_297_;
-  wire  _zz_298_;
-  wire  _zz_299_;
-  wire [0:0] _zz_300_;
-  wire [0:0] _zz_301_;
-  wire [1:0] _zz_302_;
-  wire [1:0] _zz_303_;
-  wire  _zz_304_;
-  wire [0:0] _zz_305_;
-  wire [5:0] _zz_306_;
-  wire [31:0] _zz_307_;
-  wire [31:0] _zz_308_;
-  wire [31:0] _zz_309_;
-  wire [31:0] _zz_310_;
-  wire  _zz_311_;
-  wire  _zz_312_;
-  wire [1:0] _zz_313_;
-  wire [1:0] _zz_314_;
-  wire  _zz_315_;
-  wire [0:0] _zz_316_;
-  wire [2:0] _zz_317_;
-  wire [31:0] _zz_318_;
-  wire [31:0] _zz_319_;
-  wire [31:0] _zz_320_;
-  wire [31:0] _zz_321_;
-  wire  _zz_322_;
-  wire [0:0] _zz_323_;
-  wire [0:0] _zz_324_;
-  wire [0:0] _zz_325_;
-  wire [1:0] _zz_326_;
-  wire [5:0] _zz_327_;
-  wire [5:0] _zz_328_;
-  wire  _zz_329_;
-  wire  _zz_330_;
-  wire [31:0] _zz_331_;
-  wire [31:0] _zz_332_;
-  wire [31:0] _zz_333_;
-  wire [31:0] _zz_334_;
-  wire [31:0] _zz_335_;
-  wire [31:0] _zz_336_;
-  wire [31:0] _zz_337_;
-  wire  _zz_338_;
-  wire [0:0] _zz_339_;
-  wire [2:0] _zz_340_;
-  wire [31:0] _zz_341_;
-  wire [31:0] _zz_342_;
-  wire  _zz_343_;
-  wire  _zz_344_;
-  wire [31:0] _zz_345_;
-  wire [31:0] _zz_346_;
-  wire [31:0] _zz_347_;
-  wire  _zz_348_;
-  wire [0:0] _zz_349_;
-  wire [12:0] _zz_350_;
-  wire [31:0] _zz_351_;
-  wire [31:0] _zz_352_;
-  wire [31:0] _zz_353_;
-  wire  _zz_354_;
-  wire [0:0] _zz_355_;
-  wire [6:0] _zz_356_;
-  wire [31:0] _zz_357_;
-  wire [31:0] _zz_358_;
-  wire [31:0] _zz_359_;
-  wire  _zz_360_;
-  wire [0:0] _zz_361_;
-  wire [0:0] _zz_362_;
-  wire [31:0] decode_RS1;
-  wire  execute_BRANCH_DO;
-  wire  execute_BYPASSABLE_MEMORY_STAGE;
-  wire  decode_BYPASSABLE_MEMORY_STAGE;
-  wire  decode_SRC2_FORCE_ZERO;
-  wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL;
-  wire `Src2CtrlEnum_defaultEncoding_type _zz_1_;
-  wire `Src2CtrlEnum_defaultEncoding_type _zz_2_;
-  wire `Src2CtrlEnum_defaultEncoding_type _zz_3_;
-  wire [31:0] writeBack_REGFILE_WRITE_DATA;
-  wire [31:0] execute_REGFILE_WRITE_DATA;
-  wire  decode_CSR_WRITE_OPCODE;
-  wire [31:0] execute_BRANCH_CALC;
-  wire [31:0] writeBack_FORMAL_PC_NEXT;
-  wire [31:0] memory_FORMAL_PC_NEXT;
-  wire [31:0] execute_FORMAL_PC_NEXT;
-  wire [31:0] decode_FORMAL_PC_NEXT;
-  wire  decode_SRC_LESS_UNSIGNED;
-  wire  decode_MEMORY_STORE;
-  wire [31:0] memory_MEMORY_READ_DATA;
-  wire  decode_BYPASSABLE_EXECUTE_STAGE;
-  wire  decode_IS_CSR;
-  wire [31:0] decode_RS2;
-  wire `EnvCtrlEnum_defaultEncoding_type _zz_4_;
-  wire `EnvCtrlEnum_defaultEncoding_type _zz_5_;
-  wire `EnvCtrlEnum_defaultEncoding_type _zz_6_;
-  wire `EnvCtrlEnum_defaultEncoding_type _zz_7_;
-  wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL;
-  wire `EnvCtrlEnum_defaultEncoding_type _zz_8_;
-  wire `EnvCtrlEnum_defaultEncoding_type _zz_9_;
-  wire `EnvCtrlEnum_defaultEncoding_type _zz_10_;
-  wire [1:0] memory_MEMORY_ADDRESS_LOW;
-  wire [1:0] execute_MEMORY_ADDRESS_LOW;
-  wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL;
-  wire `Src1CtrlEnum_defaultEncoding_type _zz_11_;
-  wire `Src1CtrlEnum_defaultEncoding_type _zz_12_;
-  wire `Src1CtrlEnum_defaultEncoding_type _zz_13_;
-  wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL;
-  wire `BranchCtrlEnum_defaultEncoding_type _zz_14_;
-  wire `BranchCtrlEnum_defaultEncoding_type _zz_15_;
-  wire `BranchCtrlEnum_defaultEncoding_type _zz_16_;
-  wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL;
-  wire `AluCtrlEnum_defaultEncoding_type _zz_17_;
-  wire `AluCtrlEnum_defaultEncoding_type _zz_18_;
-  wire `AluCtrlEnum_defaultEncoding_type _zz_19_;
-  wire  decode_CSR_READ_OPCODE;
-  wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL;
-  wire `ShiftCtrlEnum_defaultEncoding_type _zz_20_;
-  wire `ShiftCtrlEnum_defaultEncoding_type _zz_21_;
-  wire `ShiftCtrlEnum_defaultEncoding_type _zz_22_;
-  wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL;
-  wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_23_;
-  wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_24_;
-  wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_25_;
-  wire  execute_CSR_READ_OPCODE;
-  wire  execute_CSR_WRITE_OPCODE;
-  wire  execute_IS_CSR;
-  wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL;
-  wire `EnvCtrlEnum_defaultEncoding_type _zz_26_;
-  wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL;
-  wire `EnvCtrlEnum_defaultEncoding_type _zz_27_;
-  wire  _zz_28_;
-  wire  _zz_29_;
-  wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL;
-  wire `EnvCtrlEnum_defaultEncoding_type _zz_30_;
-  wire [31:0] memory_BRANCH_CALC;
-  wire  memory_BRANCH_DO;
-  wire [31:0] _zz_31_;
-  wire [31:0] execute_PC;
-  wire [31:0] execute_RS1;
-  wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL;
-  wire `BranchCtrlEnum_defaultEncoding_type _zz_32_;
-  wire  _zz_33_;
-  wire  decode_RS2_USE;
-  wire  decode_RS1_USE;
-  wire  execute_REGFILE_WRITE_VALID;
-  wire  execute_BYPASSABLE_EXECUTE_STAGE;
-  wire  memory_REGFILE_WRITE_VALID;
-  wire [31:0] memory_INSTRUCTION;
-  wire  memory_BYPASSABLE_MEMORY_STAGE;
-  wire  writeBack_REGFILE_WRITE_VALID;
-  reg [31:0] _zz_34_;
-  wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL;
-  wire `ShiftCtrlEnum_defaultEncoding_type _zz_35_;
-  wire  _zz_36_;
-  wire [31:0] _zz_37_;
-  wire [31:0] _zz_38_;
-  wire  execute_SRC_LESS_UNSIGNED;
-  wire  execute_SRC2_FORCE_ZERO;
-  wire  execute_SRC_USE_SUB_LESS;
-  wire [31:0] _zz_39_;
-  wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL;
-  wire `Src2CtrlEnum_defaultEncoding_type _zz_40_;
-  wire [31:0] _zz_41_;
-  wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL;
-  wire `Src1CtrlEnum_defaultEncoding_type _zz_42_;
-  wire [31:0] _zz_43_;
-  wire  decode_SRC_USE_SUB_LESS;
-  wire  decode_SRC_ADD_ZERO;
-  wire  _zz_44_;
-  wire [31:0] execute_SRC_ADD_SUB;
-  wire  execute_SRC_LESS;
-  wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL;
-  wire `AluCtrlEnum_defaultEncoding_type _zz_45_;
-  wire [31:0] _zz_46_;
-  wire [31:0] execute_SRC2;
-  wire [31:0] execute_SRC1;
-  wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL;
-  wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_47_;
-  wire [31:0] _zz_48_;
-  wire  _zz_49_;
-  reg  _zz_50_;
-  wire [31:0] _zz_51_;
-  wire [31:0] _zz_52_;
-  wire [31:0] decode_INSTRUCTION_ANTICIPATED;
-  reg  decode_REGFILE_WRITE_VALID;
-  wire  decode_LEGAL_INSTRUCTION;
-  wire  decode_INSTRUCTION_READY;
-  wire  _zz_53_;
-  wire  _zz_54_;
-  wire `EnvCtrlEnum_defaultEncoding_type _zz_55_;
-  wire  _zz_56_;
-  wire  _zz_57_;
-  wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_58_;
-  wire `BranchCtrlEnum_defaultEncoding_type _zz_59_;
-  wire `AluCtrlEnum_defaultEncoding_type _zz_60_;
-  wire  _zz_61_;
-  wire `Src2CtrlEnum_defaultEncoding_type _zz_62_;
-  wire  _zz_63_;
-  wire  _zz_64_;
-  wire `Src1CtrlEnum_defaultEncoding_type _zz_65_;
-  wire  _zz_66_;
-  wire  _zz_67_;
-  wire  _zz_68_;
-  wire  _zz_69_;
-  wire `ShiftCtrlEnum_defaultEncoding_type _zz_70_;
-  wire  _zz_71_;
-  wire  writeBack_MEMORY_STORE;
-  reg [31:0] _zz_72_;
-  wire  writeBack_MEMORY_ENABLE;
-  wire [1:0] writeBack_MEMORY_ADDRESS_LOW;
-  wire [31:0] writeBack_MEMORY_READ_DATA;
-  wire  memory_MMU_FAULT;
-  wire [31:0] memory_MMU_RSP_physicalAddress;
-  wire  memory_MMU_RSP_isIoAccess;
-  wire  memory_MMU_RSP_allowRead;
-  wire  memory_MMU_RSP_allowWrite;
-  wire  memory_MMU_RSP_allowExecute;
-  wire  memory_MMU_RSP_exception;
-  wire  memory_MMU_RSP_refilling;
-  wire [31:0] memory_PC;
-  wire  memory_ALIGNEMENT_FAULT;
-  wire [31:0] memory_REGFILE_WRITE_DATA;
-  wire  memory_MEMORY_STORE;
-  wire  memory_MEMORY_ENABLE;
-  wire [31:0] _zz_73_;
-  wire [31:0] _zz_74_;
-  wire  _zz_75_;
-  wire  _zz_76_;
-  wire  _zz_77_;
-  wire  _zz_78_;
-  wire  _zz_79_;
-  wire  _zz_80_;
-  wire  execute_MMU_FAULT;
-  wire [31:0] execute_MMU_RSP_physicalAddress;
-  wire  execute_MMU_RSP_isIoAccess;
-  wire  execute_MMU_RSP_allowRead;
-  wire  execute_MMU_RSP_allowWrite;
-  wire  execute_MMU_RSP_allowExecute;
-  wire  execute_MMU_RSP_exception;
-  wire  execute_MMU_RSP_refilling;
-  wire  _zz_81_;
-  wire [31:0] execute_SRC_ADD;
-  wire [1:0] _zz_82_;
-  wire [31:0] execute_RS2;
-  wire [31:0] execute_INSTRUCTION;
-  wire  execute_MEMORY_STORE;
-  wire  execute_MEMORY_ENABLE;
-  wire  execute_ALIGNEMENT_FAULT;
-  wire  _zz_83_;
-  wire  decode_MEMORY_ENABLE;
-  reg [31:0] _zz_84_;
-  reg [31:0] _zz_85_;
-  wire [31:0] decode_PC;
-  wire [31:0] _zz_86_;
-  wire [31:0] _zz_87_;
-  wire [31:0] _zz_88_;
-  wire [31:0] decode_INSTRUCTION;
-  wire [31:0] _zz_89_;
-  wire [31:0] writeBack_PC;
-  wire [31:0] writeBack_INSTRUCTION;
-  reg  decode_arbitration_haltItself;
-  reg  decode_arbitration_haltByOther;
-  reg  decode_arbitration_removeIt;
-  reg  decode_arbitration_flushIt;
-  reg  decode_arbitration_flushNext;
-  wire  decode_arbitration_isValid;
-  wire  decode_arbitration_isStuck;
-  wire  decode_arbitration_isStuckByOthers;
-  wire  decode_arbitration_isFlushed;
-  wire  decode_arbitration_isMoving;
-  wire  decode_arbitration_isFiring;
-  reg  execute_arbitration_haltItself;
-  wire  execute_arbitration_haltByOther;
-  reg  execute_arbitration_removeIt;
-  wire  execute_arbitration_flushIt;
-  reg  execute_arbitration_flushNext;
-  reg  execute_arbitration_isValid;
-  wire  execute_arbitration_isStuck;
-  wire  execute_arbitration_isStuckByOthers;
-  wire  execute_arbitration_isFlushed;
-  wire  execute_arbitration_isMoving;
-  wire  execute_arbitration_isFiring;
-  reg  memory_arbitration_haltItself;
-  wire  memory_arbitration_haltByOther;
-  reg  memory_arbitration_removeIt;
-  reg  memory_arbitration_flushIt;
-  reg  memory_arbitration_flushNext;
-  reg  memory_arbitration_isValid;
-  wire  memory_arbitration_isStuck;
-  wire  memory_arbitration_isStuckByOthers;
-  wire  memory_arbitration_isFlushed;
-  wire  memory_arbitration_isMoving;
-  wire  memory_arbitration_isFiring;
-  wire  writeBack_arbitration_haltItself;
-  wire  writeBack_arbitration_haltByOther;
-  reg  writeBack_arbitration_removeIt;
-  wire  writeBack_arbitration_flushIt;
-  reg  writeBack_arbitration_flushNext;
-  reg  writeBack_arbitration_isValid;
-  wire  writeBack_arbitration_isStuck;
-  wire  writeBack_arbitration_isStuckByOthers;
-  wire  writeBack_arbitration_isFlushed;
-  wire  writeBack_arbitration_isMoving;
-  wire  writeBack_arbitration_isFiring;
-  wire [31:0] lastStageInstruction /* verilator public */ ;
-  wire [31:0] lastStagePc /* verilator public */ ;
-  wire  lastStageIsValid /* verilator public */ ;
-  wire  lastStageIsFiring /* verilator public */ ;
-  reg  IBusSimplePlugin_fetcherHalt;
-  reg  IBusSimplePlugin_fetcherflushIt;
-  reg  IBusSimplePlugin_incomingInstruction;
-  wire  IBusSimplePlugin_pcValids_0;
-  wire  IBusSimplePlugin_pcValids_1;
-  wire  IBusSimplePlugin_pcValids_2;
-  wire  IBusSimplePlugin_pcValids_3;
-  wire  iBus_cmd_valid;
-  wire  iBus_cmd_ready;
-  wire [31:0] iBus_cmd_payload_pc;
-  wire  iBus_rsp_valid;
-  wire  iBus_rsp_payload_error;
-  wire [31:0] iBus_rsp_payload_inst;
-  wire  IBusSimplePlugin_decodeExceptionPort_valid;
-  reg [3:0] IBusSimplePlugin_decodeExceptionPort_payload_code;
-  wire [31:0] IBusSimplePlugin_decodeExceptionPort_payload_badAddr;
-  wire  IBusSimplePlugin_mmuBus_cmd_isValid;
-  wire [31:0] IBusSimplePlugin_mmuBus_cmd_virtualAddress;
-  wire  IBusSimplePlugin_mmuBus_cmd_bypassTranslation;
-  wire [31:0] IBusSimplePlugin_mmuBus_rsp_physicalAddress;
-  wire  IBusSimplePlugin_mmuBus_rsp_isIoAccess;
-  wire  IBusSimplePlugin_mmuBus_rsp_allowRead;
-  wire  IBusSimplePlugin_mmuBus_rsp_allowWrite;
-  wire  IBusSimplePlugin_mmuBus_rsp_allowExecute;
-  wire  IBusSimplePlugin_mmuBus_rsp_exception;
-  wire  IBusSimplePlugin_mmuBus_rsp_refilling;
-  wire  IBusSimplePlugin_mmuBus_end;
-  wire  IBusSimplePlugin_mmuBus_busy;
-  wire  IBusSimplePlugin_redoBranch_valid;
-  wire [31:0] IBusSimplePlugin_redoBranch_payload;
-  reg  DBusSimplePlugin_memoryExceptionPort_valid;
-  reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code;
-  wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr;
-  wire  DBusSimplePlugin_mmuBus_cmd_isValid;
-  wire [31:0] DBusSimplePlugin_mmuBus_cmd_virtualAddress;
-  wire  DBusSimplePlugin_mmuBus_cmd_bypassTranslation;
-  wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress;
-  wire  DBusSimplePlugin_mmuBus_rsp_isIoAccess;
-  wire  DBusSimplePlugin_mmuBus_rsp_allowRead;
-  wire  DBusSimplePlugin_mmuBus_rsp_allowWrite;
-  wire  DBusSimplePlugin_mmuBus_rsp_allowExecute;
-  wire  DBusSimplePlugin_mmuBus_rsp_exception;
-  wire  DBusSimplePlugin_mmuBus_rsp_refilling;
-  wire  DBusSimplePlugin_mmuBus_end;
-  wire  DBusSimplePlugin_mmuBus_busy;
-  reg  DBusSimplePlugin_redoBranch_valid;
-  wire [31:0] DBusSimplePlugin_redoBranch_payload;
-  wire  decodeExceptionPort_valid;
-  wire [3:0] decodeExceptionPort_payload_code;
-  wire [31:0] decodeExceptionPort_payload_badAddr;
-  wire  BranchPlugin_jumpInterface_valid;
-  wire [31:0] BranchPlugin_jumpInterface_payload;
-  wire  BranchPlugin_branchExceptionPort_valid;
-  wire [3:0] BranchPlugin_branchExceptionPort_payload_code;
-  wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr;
-  reg  CsrPlugin_jumpInterface_valid;
-  reg [31:0] CsrPlugin_jumpInterface_payload;
-  wire  CsrPlugin_exceptionPendings_0;
-  wire  CsrPlugin_exceptionPendings_1;
-  wire  CsrPlugin_exceptionPendings_2;
-  wire  CsrPlugin_exceptionPendings_3;
-  wire  externalInterrupt;
-  wire  contextSwitching;
-  reg [1:0] CsrPlugin_privilege;
-  wire  CsrPlugin_forceMachineWire;
-  reg  CsrPlugin_selfException_valid;
-  reg [3:0] CsrPlugin_selfException_payload_code;
-  wire [31:0] CsrPlugin_selfException_payload_badAddr;
-  wire  CsrPlugin_allowInterrupts;
-  wire  CsrPlugin_allowException;
-  wire  IBusSimplePlugin_jump_pcLoad_valid;
-  wire [31:0] IBusSimplePlugin_jump_pcLoad_payload;
-  wire [3:0] _zz_90_;
-  wire [3:0] _zz_91_;
-  wire  _zz_92_;
-  wire  _zz_93_;
-  wire  _zz_94_;
-  wire  IBusSimplePlugin_fetchPc_output_valid;
-  wire  IBusSimplePlugin_fetchPc_output_ready;
-  wire [31:0] IBusSimplePlugin_fetchPc_output_payload;
-  reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ;
-  reg  IBusSimplePlugin_fetchPc_corrected;
-  reg  IBusSimplePlugin_fetchPc_pcRegPropagate;
-  reg  IBusSimplePlugin_fetchPc_booted;
-  reg  IBusSimplePlugin_fetchPc_inc;
-  reg [31:0] IBusSimplePlugin_fetchPc_pc;
-  reg  IBusSimplePlugin_iBusRsp_stages_0_input_valid;
-  reg  IBusSimplePlugin_iBusRsp_stages_0_input_ready;
-  wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload;
-  wire  IBusSimplePlugin_iBusRsp_stages_0_output_valid;
-  wire  IBusSimplePlugin_iBusRsp_stages_0_output_ready;
-  wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload;
-  reg  IBusSimplePlugin_iBusRsp_stages_0_halt;
-  wire  IBusSimplePlugin_iBusRsp_stages_0_inputSample;
-  wire  IBusSimplePlugin_iBusRsp_stages_1_input_valid;
-  wire  IBusSimplePlugin_iBusRsp_stages_1_input_ready;
-  wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload;
-  wire  IBusSimplePlugin_iBusRsp_stages_1_output_valid;
-  wire  IBusSimplePlugin_iBusRsp_stages_1_output_ready;
-  wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload;
-  wire  IBusSimplePlugin_iBusRsp_stages_1_halt;
-  wire  IBusSimplePlugin_iBusRsp_stages_1_inputSample;
-  wire  _zz_95_;
-  wire  _zz_96_;
-  wire  _zz_97_;
-  wire  _zz_98_;
-  reg  _zz_99_;
-  reg  IBusSimplePlugin_iBusRsp_readyForError;
-  wire  IBusSimplePlugin_iBusRsp_inputBeforeStage_valid;
-  wire  IBusSimplePlugin_iBusRsp_inputBeforeStage_ready;
-  wire [31:0] IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc;
-  wire  IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error;
-  wire [31:0] IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst;
-  wire  IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc;
-  wire  IBusSimplePlugin_injector_decodeInput_valid;
-  wire  IBusSimplePlugin_injector_decodeInput_ready;
-  wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc;
-  wire  IBusSimplePlugin_injector_decodeInput_payload_rsp_error;
-  wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst;
-  wire  IBusSimplePlugin_injector_decodeInput_payload_isRvc;
-  reg  _zz_100_;
-  reg [31:0] _zz_101_;
-  reg  _zz_102_;
-  reg [31:0] _zz_103_;
-  reg  _zz_104_;
-  reg  IBusSimplePlugin_injector_nextPcCalc_valids_0;
-  reg  IBusSimplePlugin_injector_nextPcCalc_valids_1;
-  reg  IBusSimplePlugin_injector_nextPcCalc_valids_2;
-  reg  IBusSimplePlugin_injector_nextPcCalc_valids_3;
-  reg  IBusSimplePlugin_injector_nextPcCalc_valids_4;
-  reg  IBusSimplePlugin_injector_decodeRemoved;
-  reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode;
-  reg  IBusSimplePlugin_cmd_valid;
-  wire  IBusSimplePlugin_cmd_ready;
-  wire [31:0] IBusSimplePlugin_cmd_payload_pc;
-  reg [2:0] IBusSimplePlugin_pendingCmd;
-  wire [2:0] IBusSimplePlugin_pendingCmdNext;
-  reg [31:0] IBusSimplePlugin_mmu_joinCtx_physicalAddress;
-  reg  IBusSimplePlugin_mmu_joinCtx_isIoAccess;
-  reg  IBusSimplePlugin_mmu_joinCtx_allowRead;
-  reg  IBusSimplePlugin_mmu_joinCtx_allowWrite;
-  reg  IBusSimplePlugin_mmu_joinCtx_allowExecute;
-  reg  IBusSimplePlugin_mmu_joinCtx_exception;
-  reg  IBusSimplePlugin_mmu_joinCtx_refilling;
-  reg [2:0] IBusSimplePlugin_rspJoin_discardCounter;
-  wire  IBusSimplePlugin_rspJoin_rspBufferOutput_valid;
-  wire  IBusSimplePlugin_rspJoin_rspBufferOutput_ready;
-  wire  IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error;
-  wire [31:0] IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst;
-  wire  iBus_rsp_takeWhen_valid;
-  wire  iBus_rsp_takeWhen_payload_error;
-  wire [31:0] iBus_rsp_takeWhen_payload_inst;
-  wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc;
-  reg  IBusSimplePlugin_rspJoin_fetchRsp_rsp_error;
-  wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst;
-  wire  IBusSimplePlugin_rspJoin_fetchRsp_isRvc;
-  wire  IBusSimplePlugin_rspJoin_join_valid;
-  wire  IBusSimplePlugin_rspJoin_join_ready;
-  wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc;
-  wire  IBusSimplePlugin_rspJoin_join_payload_rsp_error;
-  wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst;
-  wire  IBusSimplePlugin_rspJoin_join_payload_isRvc;
-  reg  IBusSimplePlugin_rspJoin_exceptionDetected;
-  reg  IBusSimplePlugin_rspJoin_redoRequired;
-  wire  _zz_105_;
-  wire  dBus_cmd_valid;
-  wire  dBus_cmd_ready;
-  wire  dBus_cmd_payload_wr;
-  wire [31:0] dBus_cmd_payload_address;
-  wire [31:0] dBus_cmd_payload_data;
-  wire [1:0] dBus_cmd_payload_size;
-  wire  dBus_rsp_ready;
-  wire  dBus_rsp_error;
-  wire [31:0] dBus_rsp_data;
-  wire  _zz_106_;
-  reg  execute_DBusSimplePlugin_skipCmd;
-  reg [31:0] _zz_107_;
-  reg [3:0] _zz_108_;
-  wire [3:0] execute_DBusSimplePlugin_formalMask;
-  reg [31:0] writeBack_DBusSimplePlugin_rspShifted;
-  wire  _zz_109_;
-  reg [31:0] _zz_110_;
-  wire  _zz_111_;
-  reg [31:0] _zz_112_;
-  reg [31:0] writeBack_DBusSimplePlugin_rspFormated;
-  wire [25:0] _zz_113_;
-  wire  _zz_114_;
-  wire  _zz_115_;
-  wire  _zz_116_;
-  wire  _zz_117_;
-  wire `ShiftCtrlEnum_defaultEncoding_type _zz_118_;
-  wire `Src1CtrlEnum_defaultEncoding_type _zz_119_;
-  wire `Src2CtrlEnum_defaultEncoding_type _zz_120_;
-  wire `AluCtrlEnum_defaultEncoding_type _zz_121_;
-  wire `BranchCtrlEnum_defaultEncoding_type _zz_122_;
-  wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_123_;
-  wire `EnvCtrlEnum_defaultEncoding_type _zz_124_;
-  wire [4:0] decode_RegFilePlugin_regFileReadAddress1;
-  wire [4:0] decode_RegFilePlugin_regFileReadAddress2;
-  wire [31:0] decode_RegFilePlugin_rs1Data;
-  wire [31:0] decode_RegFilePlugin_rs2Data;
-  reg  lastStageRegFileWrite_valid /* verilator public */ ;
-  wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ;
-  wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ;
-  reg  _zz_125_;
-  reg [31:0] execute_IntAluPlugin_bitwise;
-  reg [31:0] _zz_126_;
-  reg [31:0] _zz_127_;
-  wire  _zz_128_;
-  reg [19:0] _zz_129_;
-  wire  _zz_130_;
-  reg [19:0] _zz_131_;
-  reg [31:0] _zz_132_;
-  reg [31:0] execute_SrcPlugin_addSub;
-  wire  execute_SrcPlugin_less;
-  reg  execute_LightShifterPlugin_isActive;
-  wire  execute_LightShifterPlugin_isShift;
-  reg [4:0] execute_LightShifterPlugin_amplitudeReg;
-  wire [4:0] execute_LightShifterPlugin_amplitude;
-  wire [31:0] execute_LightShifterPlugin_shiftInput;
-  wire  execute_LightShifterPlugin_done;
-  reg [31:0] _zz_133_;
-  reg  _zz_134_;
-  reg  _zz_135_;
-  wire  _zz_136_;
-  reg  _zz_137_;
-  reg [4:0] _zz_138_;
-  wire  execute_BranchPlugin_eq;
-  wire [2:0] _zz_139_;
-  reg  _zz_140_;
-  reg  _zz_141_;
-  wire [31:0] execute_BranchPlugin_branch_src1;
-  wire  _zz_142_;
-  reg [10:0] _zz_143_;
-  wire  _zz_144_;
-  reg [19:0] _zz_145_;
-  wire  _zz_146_;
-  reg [18:0] _zz_147_;
-  reg [31:0] _zz_148_;
-  wire [31:0] execute_BranchPlugin_branch_src2;
-  wire [31:0] execute_BranchPlugin_branchAdder;
-  wire [1:0] CsrPlugin_misa_base;
-  wire [25:0] CsrPlugin_misa_extensions;
-  reg [1:0] CsrPlugin_mtvec_mode;
-  reg [29:0] CsrPlugin_mtvec_base;
-  reg [31:0] CsrPlugin_mepc;
-  reg  CsrPlugin_mstatus_MIE;
-  reg  CsrPlugin_mstatus_MPIE;
-  reg [1:0] CsrPlugin_mstatus_MPP;
-  reg  CsrPlugin_mip_MEIP;
-  reg  CsrPlugin_mip_MTIP;
-  reg  CsrPlugin_mip_MSIP;
-  reg  CsrPlugin_mie_MEIE;
-  reg  CsrPlugin_mie_MTIE;
-  reg  CsrPlugin_mie_MSIE;
-  reg  CsrPlugin_mcause_interrupt;
-  reg [3:0] CsrPlugin_mcause_exceptionCode;
-  reg [31:0] CsrPlugin_mtval;
-  reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000;
-  reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000;
-  wire  _zz_149_;
-  wire  _zz_150_;
-  wire  _zz_151_;
-  reg  CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
-  reg  CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
-  reg  CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
-  reg  CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack;
-  reg  CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
-  reg  CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
-  reg  CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
-  reg  CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
-  reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code;
-  reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
-  wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped;
-  wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
-  wire [1:0] _zz_152_;
-  wire  _zz_153_;
-  wire [1:0] _zz_154_;
-  wire  _zz_155_;
-  reg  CsrPlugin_interrupt_valid;
-  reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ;
-  reg [1:0] CsrPlugin_interrupt_targetPrivilege;
-  wire  CsrPlugin_exception;
-  wire  CsrPlugin_lastStageWasWfi;
-  reg  CsrPlugin_pipelineLiberator_done;
-  wire  CsrPlugin_interruptJump /* verilator public */ ;
-  reg  CsrPlugin_hadException;
-  reg [1:0] CsrPlugin_targetPrivilege;
-  reg [3:0] CsrPlugin_trapCause;
-  reg [1:0] CsrPlugin_xtvec_mode;
-  reg [29:0] CsrPlugin_xtvec_base;
-  wire  execute_CsrPlugin_inWfi /* verilator public */ ;
-  reg  execute_CsrPlugin_wfiWake;
-  wire  execute_CsrPlugin_blockedBySideEffects;
-  reg  execute_CsrPlugin_illegalAccess;
-  reg  execute_CsrPlugin_illegalInstruction;
-  reg [31:0] execute_CsrPlugin_readData;
-  wire  execute_CsrPlugin_writeInstruction;
-  wire  execute_CsrPlugin_readInstruction;
-  wire  execute_CsrPlugin_writeEnable;
-  wire  execute_CsrPlugin_readEnable;
-  wire [31:0] execute_CsrPlugin_readToWriteData;
-  reg [31:0] execute_CsrPlugin_writeData;
-  wire [11:0] execute_CsrPlugin_csrAddress;
-  reg [31:0] externalInterruptArray_regNext;
-  reg [31:0] _zz_156_;
-  wire [31:0] _zz_157_;
-  reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL;
-  reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL;
-  reg  decode_to_execute_SRC_USE_SUB_LESS;
-  reg  execute_to_memory_MMU_FAULT;
-  reg  decode_to_execute_CSR_READ_OPCODE;
-  reg [31:0] execute_to_memory_MMU_RSP_physicalAddress;
-  reg  execute_to_memory_MMU_RSP_isIoAccess;
-  reg  execute_to_memory_MMU_RSP_allowRead;
-  reg  execute_to_memory_MMU_RSP_allowWrite;
-  reg  execute_to_memory_MMU_RSP_allowExecute;
-  reg  execute_to_memory_MMU_RSP_exception;
-  reg  execute_to_memory_MMU_RSP_refilling;
-  reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL;
-  reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL;
-  reg  execute_to_memory_ALIGNEMENT_FAULT;
-  reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL;
-  reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW;
-  reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW;
-  reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL;
-  reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL;
-  reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL;
-  reg [31:0] decode_to_execute_RS2;
-  reg  decode_to_execute_IS_CSR;
-  reg  decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
-  reg [31:0] memory_to_writeBack_MEMORY_READ_DATA;
-  reg  decode_to_execute_MEMORY_STORE;
-  reg  execute_to_memory_MEMORY_STORE;
-  reg  memory_to_writeBack_MEMORY_STORE;
-  reg  decode_to_execute_SRC_LESS_UNSIGNED;
-  reg [31:0] decode_to_execute_FORMAL_PC_NEXT;
-  reg [31:0] execute_to_memory_FORMAL_PC_NEXT;
-  reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT;
-  reg  decode_to_execute_MEMORY_ENABLE;
-  reg  execute_to_memory_MEMORY_ENABLE;
-  reg  memory_to_writeBack_MEMORY_ENABLE;
-  reg [31:0] decode_to_execute_PC;
-  reg [31:0] execute_to_memory_PC;
-  reg [31:0] memory_to_writeBack_PC;
-  reg [31:0] execute_to_memory_BRANCH_CALC;
-  reg  decode_to_execute_CSR_WRITE_OPCODE;
-  reg [31:0] execute_to_memory_REGFILE_WRITE_DATA;
-  reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA;
-  reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL;
-  reg  decode_to_execute_SRC2_FORCE_ZERO;
-  reg [31:0] decode_to_execute_INSTRUCTION;
-  reg [31:0] execute_to_memory_INSTRUCTION;
-  reg [31:0] memory_to_writeBack_INSTRUCTION;
-  reg  decode_to_execute_BYPASSABLE_MEMORY_STAGE;
-  reg  execute_to_memory_BYPASSABLE_MEMORY_STAGE;
-  reg  execute_to_memory_BRANCH_DO;
-  reg [31:0] decode_to_execute_RS1;
-  reg  decode_to_execute_REGFILE_WRITE_VALID;
-  reg  execute_to_memory_REGFILE_WRITE_VALID;
-  reg  memory_to_writeBack_REGFILE_WRITE_VALID;
-  wire  iBus_cmd_m2sPipe_valid;
-  wire  iBus_cmd_m2sPipe_ready;
-  wire [31:0] iBus_cmd_m2sPipe_payload_pc;
-  reg  _zz_158_;
-  reg [31:0] _zz_159_;
-  wire  dBus_cmd_halfPipe_valid;
-  wire  dBus_cmd_halfPipe_ready;
-  wire  dBus_cmd_halfPipe_payload_wr;
-  wire [31:0] dBus_cmd_halfPipe_payload_address;
-  wire [31:0] dBus_cmd_halfPipe_payload_data;
-  wire [1:0] dBus_cmd_halfPipe_payload_size;
-  reg  dBus_cmd_halfPipe_regs_valid;
-  reg  dBus_cmd_halfPipe_regs_ready;
-  reg  dBus_cmd_halfPipe_regs_payload_wr;
-  reg [31:0] dBus_cmd_halfPipe_regs_payload_address;
-  reg [31:0] dBus_cmd_halfPipe_regs_payload_data;
-  reg [1:0] dBus_cmd_halfPipe_regs_payload_size;
-  reg [3:0] _zz_160_;
-  `ifndef SYNTHESIS
-  reg [23:0] decode_SRC2_CTRL_string;
-  reg [23:0] _zz_1__string;
-  reg [23:0] _zz_2__string;
-  reg [23:0] _zz_3__string;
-  reg [39:0] _zz_4__string;
-  reg [39:0] _zz_5__string;
-  reg [39:0] _zz_6__string;
-  reg [39:0] _zz_7__string;
-  reg [39:0] decode_ENV_CTRL_string;
-  reg [39:0] _zz_8__string;
-  reg [39:0] _zz_9__string;
-  reg [39:0] _zz_10__string;
-  reg [95:0] decode_SRC1_CTRL_string;
-  reg [95:0] _zz_11__string;
-  reg [95:0] _zz_12__string;
-  reg [95:0] _zz_13__string;
-  reg [31:0] decode_BRANCH_CTRL_string;
-  reg [31:0] _zz_14__string;
-  reg [31:0] _zz_15__string;
-  reg [31:0] _zz_16__string;
-  reg [63:0] decode_ALU_CTRL_string;
-  reg [63:0] _zz_17__string;
-  reg [63:0] _zz_18__string;
-  reg [63:0] _zz_19__string;
-  reg [71:0] decode_SHIFT_CTRL_string;
-  reg [71:0] _zz_20__string;
-  reg [71:0] _zz_21__string;
-  reg [71:0] _zz_22__string;
-  reg [39:0] decode_ALU_BITWISE_CTRL_string;
-  reg [39:0] _zz_23__string;
-  reg [39:0] _zz_24__string;
-  reg [39:0] _zz_25__string;
-  reg [39:0] memory_ENV_CTRL_string;
-  reg [39:0] _zz_26__string;
-  reg [39:0] execute_ENV_CTRL_string;
-  reg [39:0] _zz_27__string;
-  reg [39:0] writeBack_ENV_CTRL_string;
-  reg [39:0] _zz_30__string;
-  reg [31:0] execute_BRANCH_CTRL_string;
-  reg [31:0] _zz_32__string;
-  reg [71:0] execute_SHIFT_CTRL_string;
-  reg [71:0] _zz_35__string;
-  reg [23:0] execute_SRC2_CTRL_string;
-  reg [23:0] _zz_40__string;
-  reg [95:0] execute_SRC1_CTRL_string;
-  reg [95:0] _zz_42__string;
-  reg [63:0] execute_ALU_CTRL_string;
-  reg [63:0] _zz_45__string;
-  reg [39:0] execute_ALU_BITWISE_CTRL_string;
-  reg [39:0] _zz_47__string;
-  reg [39:0] _zz_55__string;
-  reg [39:0] _zz_58__string;
-  reg [31:0] _zz_59__string;
-  reg [63:0] _zz_60__string;
-  reg [23:0] _zz_62__string;
-  reg [95:0] _zz_65__string;
-  reg [71:0] _zz_70__string;
-  reg [71:0] _zz_118__string;
-  reg [95:0] _zz_119__string;
-  reg [23:0] _zz_120__string;
-  reg [63:0] _zz_121__string;
-  reg [31:0] _zz_122__string;
-  reg [39:0] _zz_123__string;
-  reg [39:0] _zz_124__string;
-  reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string;
-  reg [71:0] decode_to_execute_SHIFT_CTRL_string;
-  reg [63:0] decode_to_execute_ALU_CTRL_string;
-  reg [31:0] decode_to_execute_BRANCH_CTRL_string;
-  reg [95:0] decode_to_execute_SRC1_CTRL_string;
-  reg [39:0] decode_to_execute_ENV_CTRL_string;
-  reg [39:0] execute_to_memory_ENV_CTRL_string;
-  reg [39:0] memory_to_writeBack_ENV_CTRL_string;
-  reg [23:0] decode_to_execute_SRC2_CTRL_string;
-  `endif
-
-  (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;
-  assign _zz_164_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000)));
-  assign _zz_165_ = (execute_arbitration_isValid && execute_IS_CSR);
-  assign _zz_166_ = ({decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid} != (2'b00));
-  assign _zz_167_ = (! execute_arbitration_isStuckByOthers);
-  assign _zz_168_ = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != (2'b00));
-  assign _zz_169_ = (CsrPlugin_hadException || CsrPlugin_interruptJump);
-  assign _zz_170_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET));
-  assign _zz_171_ = writeBack_INSTRUCTION[29 : 28];
-  assign _zz_172_ = (IBusSimplePlugin_mmuBus_rsp_exception || IBusSimplePlugin_mmuBus_rsp_refilling);
-  assign _zz_173_ = ((IBusSimplePlugin_iBusRsp_stages_1_input_valid && (! IBusSimplePlugin_mmu_joinCtx_refilling)) && (IBusSimplePlugin_mmu_joinCtx_exception || (! IBusSimplePlugin_mmu_joinCtx_allowExecute)));
-  assign _zz_174_ = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE));
-  assign _zz_175_ = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers))));
-  assign _zz_176_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
-  assign _zz_177_ = (1'b1 || (! 1'b1));
-  assign _zz_178_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
-  assign _zz_179_ = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE));
-  assign _zz_180_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
-  assign _zz_181_ = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE));
-  assign _zz_182_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL));
-  assign _zz_183_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11)));
-  assign _zz_184_ = ((_zz_149_ && 1'b1) && (! 1'b0));
-  assign _zz_185_ = ((_zz_150_ && 1'b1) && (! 1'b0));
-  assign _zz_186_ = ((_zz_151_ && 1'b1) && (! 1'b0));
-  assign _zz_187_ = (! dBus_cmd_halfPipe_regs_valid);
-  assign _zz_188_ = writeBack_INSTRUCTION[13 : 12];
-  assign _zz_189_ = execute_INSTRUCTION[13];
-  assign _zz_190_ = (_zz_90_ - (4'b0001));
-  assign _zz_191_ = {IBusSimplePlugin_fetchPc_inc,(2'b00)};
-  assign _zz_192_ = {29'd0, _zz_191_};
-  assign _zz_193_ = (IBusSimplePlugin_pendingCmd + _zz_195_);
-  assign _zz_194_ = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready);
-  assign _zz_195_ = {2'd0, _zz_194_};
-  assign _zz_196_ = iBus_rsp_valid;
-  assign _zz_197_ = {2'd0, _zz_196_};
-  assign _zz_198_ = (iBus_rsp_valid && (IBusSimplePlugin_rspJoin_discardCounter != (3'b000)));
-  assign _zz_199_ = {2'd0, _zz_198_};
-  assign _zz_200_ = iBus_rsp_valid;
-  assign _zz_201_ = {2'd0, _zz_200_};
-  assign _zz_202_ = (memory_MEMORY_STORE ? (3'b110) : (3'b100));
-  assign _zz_203_ = _zz_113_[2 : 2];
-  assign _zz_204_ = _zz_113_[4 : 4];
-  assign _zz_205_ = _zz_113_[5 : 5];
-  assign _zz_206_ = _zz_113_[6 : 6];
-  assign _zz_207_ = _zz_113_[9 : 9];
-  assign _zz_208_ = _zz_113_[10 : 10];
-  assign _zz_209_ = _zz_113_[13 : 13];
-  assign _zz_210_ = _zz_113_[20 : 20];
-  assign _zz_211_ = _zz_113_[21 : 21];
-  assign _zz_212_ = _zz_113_[24 : 24];
-  assign _zz_213_ = _zz_113_[25 : 25];
-  assign _zz_214_ = execute_SRC_LESS;
-  assign _zz_215_ = (3'b100);
-  assign _zz_216_ = execute_INSTRUCTION[19 : 15];
-  assign _zz_217_ = execute_INSTRUCTION[31 : 20];
-  assign _zz_218_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]};
-  assign _zz_219_ = ($signed(_zz_220_) + $signed(_zz_223_));
-  assign _zz_220_ = ($signed(_zz_221_) + $signed(_zz_222_));
-  assign _zz_221_ = execute_SRC1;
-  assign _zz_222_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2);
-  assign _zz_223_ = (execute_SRC_USE_SUB_LESS ? _zz_224_ : _zz_225_);
-  assign _zz_224_ = (32'b00000000000000000000000000000001);
-  assign _zz_225_ = (32'b00000000000000000000000000000000);
-  assign _zz_226_ = (_zz_227_ >>> 1);
-  assign _zz_227_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput};
-  assign _zz_228_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
-  assign _zz_229_ = execute_INSTRUCTION[31 : 20];
-  assign _zz_230_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
-  assign _zz_231_ = (_zz_152_ & (~ _zz_232_));
-  assign _zz_232_ = (_zz_152_ - (2'b01));
-  assign _zz_233_ = (_zz_154_ & (~ _zz_234_));
-  assign _zz_234_ = (_zz_154_ - (2'b01));
-  assign _zz_235_ = execute_CsrPlugin_writeData[7 : 7];
-  assign _zz_236_ = execute_CsrPlugin_writeData[3 : 3];
-  assign _zz_237_ = execute_CsrPlugin_writeData[3 : 3];
-  assign _zz_238_ = execute_CsrPlugin_writeData[11 : 11];
-  assign _zz_239_ = execute_CsrPlugin_writeData[7 : 7];
-  assign _zz_240_ = execute_CsrPlugin_writeData[3 : 3];
-  assign _zz_241_ = ({3'd0,_zz_160_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]);
-  assign _zz_242_ = 1'b1;
-  assign _zz_243_ = 1'b1;
-  assign _zz_244_ = {_zz_94_,_zz_93_};
-  assign _zz_245_ = (32'b00000000000000000000000000010000);
-  assign _zz_246_ = (decode_INSTRUCTION & (32'b00010000000000000011000001010000));
-  assign _zz_247_ = (32'b00000000000000000000000001010000);
-  assign _zz_248_ = ((decode_INSTRUCTION & (32'b00010000010000000011000001010000)) == (32'b00010000000000000000000001010000));
-  assign _zz_249_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000100000));
-  assign _zz_250_ = (1'b0);
-  assign _zz_251_ = ({(_zz_254_ == _zz_255_),(_zz_256_ == _zz_257_)} != (2'b00));
-  assign _zz_252_ = ((_zz_258_ == _zz_259_) != (1'b0));
-  assign _zz_253_ = {(_zz_260_ != (1'b0)),{(_zz_261_ != _zz_262_),{_zz_263_,{_zz_264_,_zz_265_}}}};
-  assign _zz_254_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100));
-  assign _zz_255_ = (32'b00000000000000000000000000100100);
-  assign _zz_256_ = (decode_INSTRUCTION & (32'b00000000000000000011000001010100));
-  assign _zz_257_ = (32'b00000000000000000001000000010000);
-  assign _zz_258_ = (decode_INSTRUCTION & (32'b00000000000000000001000000000000));
-  assign _zz_259_ = (32'b00000000000000000001000000000000);
-  assign _zz_260_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000));
-  assign _zz_261_ = {_zz_115_,(_zz_266_ == _zz_267_)};
-  assign _zz_262_ = (2'b00);
-  assign _zz_263_ = ((_zz_268_ == _zz_269_) != (1'b0));
-  assign _zz_264_ = ({_zz_270_,_zz_271_} != (2'b00));
-  assign _zz_265_ = {(_zz_272_ != _zz_273_),{_zz_274_,{_zz_275_,_zz_276_}}};
-  assign _zz_266_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011100));
-  assign _zz_267_ = (32'b00000000000000000000000000000100);
-  assign _zz_268_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000));
-  assign _zz_269_ = (32'b00000000000000000000000001000000);
-  assign _zz_270_ = ((decode_INSTRUCTION & _zz_277_) == (32'b00000000000000000110000000010000));
-  assign _zz_271_ = ((decode_INSTRUCTION & _zz_278_) == (32'b00000000000000000100000000010000));
-  assign _zz_272_ = ((decode_INSTRUCTION & _zz_279_) == (32'b00000000000000000010000000010000));
-  assign _zz_273_ = (1'b0);
-  assign _zz_274_ = ({_zz_280_,{_zz_281_,_zz_282_}} != (4'b0000));
-  assign _zz_275_ = ({_zz_283_,_zz_284_} != (2'b00));
-  assign _zz_276_ = {(_zz_285_ != _zz_286_),{_zz_287_,{_zz_288_,_zz_289_}}};
-  assign _zz_277_ = (32'b00000000000000000110000000010100);
-  assign _zz_278_ = (32'b00000000000000000101000000010100);
-  assign _zz_279_ = (32'b00000000000000000110000000010100);
-  assign _zz_280_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000000));
-  assign _zz_281_ = ((decode_INSTRUCTION & _zz_290_) == (32'b00000000000000000000000000000000));
-  assign _zz_282_ = {(_zz_291_ == _zz_292_),(_zz_293_ == _zz_294_)};
-  assign _zz_283_ = _zz_117_;
-  assign _zz_284_ = ((decode_INSTRUCTION & _zz_295_) == (32'b00000000000000000000000000100000));
-  assign _zz_285_ = {_zz_117_,(_zz_296_ == _zz_297_)};
-  assign _zz_286_ = (2'b00);
-  assign _zz_287_ = ({_zz_298_,_zz_299_} != (2'b00));
-  assign _zz_288_ = ({_zz_300_,_zz_301_} != (2'b00));
-  assign _zz_289_ = {(_zz_302_ != _zz_303_),{_zz_304_,{_zz_305_,_zz_306_}}};
-  assign _zz_290_ = (32'b00000000000000000000000000011000);
-  assign _zz_291_ = (decode_INSTRUCTION & (32'b00000000000000000110000000000100));
-  assign _zz_292_ = (32'b00000000000000000010000000000000);
-  assign _zz_293_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100));
-  assign _zz_294_ = (32'b00000000000000000001000000000000);
-  assign _zz_295_ = (32'b00000000000000000000000001110000);
-  assign _zz_296_ = (decode_INSTRUCTION & (32'b00000000000000000000000000100000));
-  assign _zz_297_ = (32'b00000000000000000000000000000000);
-  assign _zz_298_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000000000));
-  assign _zz_299_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000000)) == (32'b00000000000000000001000000000000));
-  assign _zz_300_ = ((decode_INSTRUCTION & _zz_307_) == (32'b00000000000000000001000001010000));
-  assign _zz_301_ = ((decode_INSTRUCTION & _zz_308_) == (32'b00000000000000000010000001010000));
-  assign _zz_302_ = {(_zz_309_ == _zz_310_),_zz_116_};
-  assign _zz_303_ = (2'b00);
-  assign _zz_304_ = ({_zz_311_,_zz_116_} != (2'b00));
-  assign _zz_305_ = (_zz_312_ != (1'b0));
-  assign _zz_306_ = {(_zz_313_ != _zz_314_),{_zz_315_,{_zz_316_,_zz_317_}}};
-  assign _zz_307_ = (32'b00000000000000000001000001010000);
-  assign _zz_308_ = (32'b00000000000000000010000001010000);
-  assign _zz_309_ = (decode_INSTRUCTION & (32'b00000000000000000000000000010100));
-  assign _zz_310_ = (32'b00000000000000000000000000000100);
-  assign _zz_311_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000100));
-  assign _zz_312_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000000000000));
-  assign _zz_313_ = {(_zz_318_ == _zz_319_),(_zz_320_ == _zz_321_)};
-  assign _zz_314_ = (2'b00);
-  assign _zz_315_ = ({_zz_322_,{_zz_323_,_zz_324_}} != (3'b000));
-  assign _zz_316_ = ({_zz_325_,_zz_326_} != (3'b000));
-  assign _zz_317_ = {(_zz_327_ != _zz_328_),{_zz_329_,_zz_330_}};
-  assign _zz_318_ = (decode_INSTRUCTION & (32'b00000000000000000000000000110100));
-  assign _zz_319_ = (32'b00000000000000000000000000100000);
-  assign _zz_320_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100));
-  assign _zz_321_ = (32'b00000000000000000000000000100000);
-  assign _zz_322_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000001000000));
-  assign _zz_323_ = ((decode_INSTRUCTION & _zz_331_) == (32'b00000000000000000010000000010000));
-  assign _zz_324_ = ((decode_INSTRUCTION & _zz_332_) == (32'b01000000000000000000000000110000));
-  assign _zz_325_ = ((decode_INSTRUCTION & _zz_333_) == (32'b00000000000000000000000001000000));
-  assign _zz_326_ = {(_zz_334_ == _zz_335_),(_zz_336_ == _zz_337_)};
-  assign _zz_327_ = {_zz_115_,{_zz_338_,{_zz_339_,_zz_340_}}};
-  assign _zz_328_ = (6'b000000);
-  assign _zz_329_ = ((_zz_341_ == _zz_342_) != (1'b0));
-  assign _zz_330_ = ({_zz_343_,_zz_344_} != (2'b00));
-  assign _zz_331_ = (32'b00000000000000000010000000010100);
-  assign _zz_332_ = (32'b01000000000000000100000000110100);
-  assign _zz_333_ = (32'b00000000000000000000000001010000);
-  assign _zz_334_ = (decode_INSTRUCTION & (32'b00000000000000000000000000111000));
-  assign _zz_335_ = (32'b00000000000000000000000000000000);
-  assign _zz_336_ = (decode_INSTRUCTION & (32'b00000000010000000011000001000000));
-  assign _zz_337_ = (32'b00000000000000000000000001000000);
-  assign _zz_338_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000010000)) == (32'b00000000000000000001000000010000));
-  assign _zz_339_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000010000));
-  assign _zz_340_ = {_zz_114_,{((decode_INSTRUCTION & (32'b00000000000000000000000000001100)) == (32'b00000000000000000000000000000100)),((decode_INSTRUCTION & (32'b00000000000000000000000000101000)) == (32'b00000000000000000000000000000000))}};
-  assign _zz_341_ = (decode_INSTRUCTION & (32'b00000000000000000111000001010100));
-  assign _zz_342_ = (32'b00000000000000000101000000010000);
-  assign _zz_343_ = ((decode_INSTRUCTION & (32'b01000000000000000011000001010100)) == (32'b01000000000000000001000000010000));
-  assign _zz_344_ = ((decode_INSTRUCTION & (32'b00000000000000000111000001010100)) == (32'b00000000000000000001000000010000));
-  assign _zz_345_ = (32'b00000000000000000001000001111111);
-  assign _zz_346_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111));
-  assign _zz_347_ = (32'b00000000000000000010000001110011);
-  assign _zz_348_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011));
-  assign _zz_349_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011));
-  assign _zz_350_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_351_) == (32'b00000000000000000000000000000011)),{(_zz_352_ == _zz_353_),{_zz_354_,{_zz_355_,_zz_356_}}}}}};
-  assign _zz_351_ = (32'b00000000000000000101000001011111);
-  assign _zz_352_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011));
-  assign _zz_353_ = (32'b00000000000000000000000001100011);
-  assign _zz_354_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111));
-  assign _zz_355_ = ((decode_INSTRUCTION & (32'b11111110000000000000000001111111)) == (32'b00000000000000000000000000110011));
-  assign _zz_356_ = {((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & (32'b11111100000000000011000001111111)) == (32'b00000000000000000001000000010011)),{((decode_INSTRUCTION & _zz_357_) == (32'b00000000000000000101000000110011)),{(_zz_358_ == _zz_359_),{_zz_360_,{_zz_361_,_zz_362_}}}}}};
-  assign _zz_357_ = (32'b10111110000000000111000001111111);
-  assign _zz_358_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111));
-  assign _zz_359_ = (32'b00000000000000000000000000110011);
-  assign _zz_360_ = ((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011));
-  assign _zz_361_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011));
-  assign _zz_362_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00000000000000000000000001110011));
-  always @ (posedge clk) begin
-    if(_zz_50_) begin
-      RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data;
-    end
-  end
-
-  always @ (posedge clk) begin
-    if(_zz_242_) begin
-      _zz_161_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1];
-    end
-  end
-
-  always @ (posedge clk) begin
-    if(_zz_243_) begin
-      _zz_162_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2];
-    end
-  end
-
-  StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c ( 
-    .io_push_valid(iBus_rsp_takeWhen_valid),
-    .io_push_ready(IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready),
-    .io_push_payload_error(iBus_rsp_takeWhen_payload_error),
-    .io_push_payload_inst(iBus_rsp_takeWhen_payload_inst),
-    .io_pop_valid(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid),
-    .io_pop_ready(IBusSimplePlugin_rspJoin_rspBufferOutput_ready),
-    .io_pop_payload_error(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error),
-    .io_pop_payload_inst(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst),
-    .io_flush(IBusSimplePlugin_fetcherflushIt),
-    .io_occupancy(IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy),
-    .clk(clk),
-    .reset(reset) 
-  );
-  always @(*) begin
-    case(_zz_244_)
-      2'b00 : begin
-        _zz_163_ = CsrPlugin_jumpInterface_payload;
-      end
-      2'b01 : begin
-        _zz_163_ = DBusSimplePlugin_redoBranch_payload;
-      end
-      2'b10 : begin
-        _zz_163_ = BranchPlugin_jumpInterface_payload;
-      end
-      default : begin
-        _zz_163_ = IBusSimplePlugin_redoBranch_payload;
-      end
-    endcase
-  end
-
-  `ifndef SYNTHESIS
-  always @(*) begin
-    case(decode_SRC2_CTRL)
-      `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS ";
-      `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI";
-      `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS";
-      `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC ";
-      default : decode_SRC2_CTRL_string = "???";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_1_)
-      `Src2CtrlEnum_defaultEncoding_RS : _zz_1__string = "RS ";
-      `Src2CtrlEnum_defaultEncoding_IMI : _zz_1__string = "IMI";
-      `Src2CtrlEnum_defaultEncoding_IMS : _zz_1__string = "IMS";
-      `Src2CtrlEnum_defaultEncoding_PC : _zz_1__string = "PC ";
-      default : _zz_1__string = "???";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_2_)
-      `Src2CtrlEnum_defaultEncoding_RS : _zz_2__string = "RS ";
-      `Src2CtrlEnum_defaultEncoding_IMI : _zz_2__string = "IMI";
-      `Src2CtrlEnum_defaultEncoding_IMS : _zz_2__string = "IMS";
-      `Src2CtrlEnum_defaultEncoding_PC : _zz_2__string = "PC ";
-      default : _zz_2__string = "???";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_3_)
-      `Src2CtrlEnum_defaultEncoding_RS : _zz_3__string = "RS ";
-      `Src2CtrlEnum_defaultEncoding_IMI : _zz_3__string = "IMI";
-      `Src2CtrlEnum_defaultEncoding_IMS : _zz_3__string = "IMS";
-      `Src2CtrlEnum_defaultEncoding_PC : _zz_3__string = "PC ";
-      default : _zz_3__string = "???";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_4_)
-      `EnvCtrlEnum_defaultEncoding_NONE : _zz_4__string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : _zz_4__string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4__string = "ECALL";
-      default : _zz_4__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_5_)
-      `EnvCtrlEnum_defaultEncoding_NONE : _zz_5__string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : _zz_5__string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5__string = "ECALL";
-      default : _zz_5__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_6_)
-      `EnvCtrlEnum_defaultEncoding_NONE : _zz_6__string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : _zz_6__string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6__string = "ECALL";
-      default : _zz_6__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_7_)
-      `EnvCtrlEnum_defaultEncoding_NONE : _zz_7__string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : _zz_7__string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7__string = "ECALL";
-      default : _zz_7__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(decode_ENV_CTRL)
-      `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL";
-      default : decode_ENV_CTRL_string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_8_)
-      `EnvCtrlEnum_defaultEncoding_NONE : _zz_8__string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : _zz_8__string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8__string = "ECALL";
-      default : _zz_8__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_9_)
-      `EnvCtrlEnum_defaultEncoding_NONE : _zz_9__string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : _zz_9__string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9__string = "ECALL";
-      default : _zz_9__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_10_)
-      `EnvCtrlEnum_defaultEncoding_NONE : _zz_10__string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : _zz_10__string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10__string = "ECALL";
-      default : _zz_10__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(decode_SRC1_CTRL)
-      `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS          ";
-      `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU         ";
-      `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT";
-      `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1        ";
-      default : decode_SRC1_CTRL_string = "????????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_11_)
-      `Src1CtrlEnum_defaultEncoding_RS : _zz_11__string = "RS          ";
-      `Src1CtrlEnum_defaultEncoding_IMU : _zz_11__string = "IMU         ";
-      `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_11__string = "PC_INCREMENT";
-      `Src1CtrlEnum_defaultEncoding_URS1 : _zz_11__string = "URS1        ";
-      default : _zz_11__string = "????????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_12_)
-      `Src1CtrlEnum_defaultEncoding_RS : _zz_12__string = "RS          ";
-      `Src1CtrlEnum_defaultEncoding_IMU : _zz_12__string = "IMU         ";
-      `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_12__string = "PC_INCREMENT";
-      `Src1CtrlEnum_defaultEncoding_URS1 : _zz_12__string = "URS1        ";
-      default : _zz_12__string = "????????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_13_)
-      `Src1CtrlEnum_defaultEncoding_RS : _zz_13__string = "RS          ";
-      `Src1CtrlEnum_defaultEncoding_IMU : _zz_13__string = "IMU         ";
-      `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_13__string = "PC_INCREMENT";
-      `Src1CtrlEnum_defaultEncoding_URS1 : _zz_13__string = "URS1        ";
-      default : _zz_13__string = "????????????";
-    endcase
-  end
-  always @(*) begin
-    case(decode_BRANCH_CTRL)
-      `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC ";
-      `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B   ";
-      `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL ";
-      `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR";
-      default : decode_BRANCH_CTRL_string = "????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_14_)
-      `BranchCtrlEnum_defaultEncoding_INC : _zz_14__string = "INC ";
-      `BranchCtrlEnum_defaultEncoding_B : _zz_14__string = "B   ";
-      `BranchCtrlEnum_defaultEncoding_JAL : _zz_14__string = "JAL ";
-      `BranchCtrlEnum_defaultEncoding_JALR : _zz_14__string = "JALR";
-      default : _zz_14__string = "????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_15_)
-      `BranchCtrlEnum_defaultEncoding_INC : _zz_15__string = "INC ";
-      `BranchCtrlEnum_defaultEncoding_B : _zz_15__string = "B   ";
-      `BranchCtrlEnum_defaultEncoding_JAL : _zz_15__string = "JAL ";
-      `BranchCtrlEnum_defaultEncoding_JALR : _zz_15__string = "JALR";
-      default : _zz_15__string = "????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_16_)
-      `BranchCtrlEnum_defaultEncoding_INC : _zz_16__string = "INC ";
-      `BranchCtrlEnum_defaultEncoding_B : _zz_16__string = "B   ";
-      `BranchCtrlEnum_defaultEncoding_JAL : _zz_16__string = "JAL ";
-      `BranchCtrlEnum_defaultEncoding_JALR : _zz_16__string = "JALR";
-      default : _zz_16__string = "????";
-    endcase
-  end
-  always @(*) begin
-    case(decode_ALU_CTRL)
-      `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB ";
-      `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU";
-      `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE ";
-      default : decode_ALU_CTRL_string = "????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_17_)
-      `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_17__string = "ADD_SUB ";
-      `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_17__string = "SLT_SLTU";
-      `AluCtrlEnum_defaultEncoding_BITWISE : _zz_17__string = "BITWISE ";
-      default : _zz_17__string = "????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_18_)
-      `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_18__string = "ADD_SUB ";
-      `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_18__string = "SLT_SLTU";
-      `AluCtrlEnum_defaultEncoding_BITWISE : _zz_18__string = "BITWISE ";
-      default : _zz_18__string = "????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_19_)
-      `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_19__string = "ADD_SUB ";
-      `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_19__string = "SLT_SLTU";
-      `AluCtrlEnum_defaultEncoding_BITWISE : _zz_19__string = "BITWISE ";
-      default : _zz_19__string = "????????";
-    endcase
-  end
-  always @(*) begin
-    case(decode_SHIFT_CTRL)
-      `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1";
-      `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1    ";
-      default : decode_SHIFT_CTRL_string = "?????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_20_)
-      `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_20__string = "DISABLE_1";
-      `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_20__string = "SLL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_20__string = "SRL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_20__string = "SRA_1    ";
-      default : _zz_20__string = "?????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_21_)
-      `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_21__string = "DISABLE_1";
-      `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_21__string = "SLL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_21__string = "SRL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_21__string = "SRA_1    ";
-      default : _zz_21__string = "?????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_22_)
-      `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_22__string = "DISABLE_1";
-      `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_22__string = "SLL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_22__string = "SRL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_22__string = "SRA_1    ";
-      default : _zz_22__string = "?????????";
-    endcase
-  end
-  always @(*) begin
-    case(decode_ALU_BITWISE_CTRL)
-      `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1";
-      `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 ";
-      `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1";
-      default : decode_ALU_BITWISE_CTRL_string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_23_)
-      `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_23__string = "XOR_1";
-      `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_23__string = "OR_1 ";
-      `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_23__string = "AND_1";
-      default : _zz_23__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_24_)
-      `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_24__string = "XOR_1";
-      `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_24__string = "OR_1 ";
-      `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_24__string = "AND_1";
-      default : _zz_24__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_25_)
-      `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_25__string = "XOR_1";
-      `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_25__string = "OR_1 ";
-      `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_25__string = "AND_1";
-      default : _zz_25__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(memory_ENV_CTRL)
-      `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL";
-      default : memory_ENV_CTRL_string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_26_)
-      `EnvCtrlEnum_defaultEncoding_NONE : _zz_26__string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : _zz_26__string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : _zz_26__string = "ECALL";
-      default : _zz_26__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(execute_ENV_CTRL)
-      `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL";
-      default : execute_ENV_CTRL_string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_27_)
-      `EnvCtrlEnum_defaultEncoding_NONE : _zz_27__string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : _zz_27__string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27__string = "ECALL";
-      default : _zz_27__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(writeBack_ENV_CTRL)
-      `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL";
-      default : writeBack_ENV_CTRL_string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_30_)
-      `EnvCtrlEnum_defaultEncoding_NONE : _zz_30__string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : _zz_30__string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : _zz_30__string = "ECALL";
-      default : _zz_30__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(execute_BRANCH_CTRL)
-      `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC ";
-      `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B   ";
-      `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL ";
-      `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR";
-      default : execute_BRANCH_CTRL_string = "????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_32_)
-      `BranchCtrlEnum_defaultEncoding_INC : _zz_32__string = "INC ";
-      `BranchCtrlEnum_defaultEncoding_B : _zz_32__string = "B   ";
-      `BranchCtrlEnum_defaultEncoding_JAL : _zz_32__string = "JAL ";
-      `BranchCtrlEnum_defaultEncoding_JALR : _zz_32__string = "JALR";
-      default : _zz_32__string = "????";
-    endcase
-  end
-  always @(*) begin
-    case(execute_SHIFT_CTRL)
-      `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1";
-      `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1    ";
-      default : execute_SHIFT_CTRL_string = "?????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_35_)
-      `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_35__string = "DISABLE_1";
-      `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_35__string = "SLL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_35__string = "SRL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_35__string = "SRA_1    ";
-      default : _zz_35__string = "?????????";
-    endcase
-  end
-  always @(*) begin
-    case(execute_SRC2_CTRL)
-      `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS ";
-      `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI";
-      `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS";
-      `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC ";
-      default : execute_SRC2_CTRL_string = "???";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_40_)
-      `Src2CtrlEnum_defaultEncoding_RS : _zz_40__string = "RS ";
-      `Src2CtrlEnum_defaultEncoding_IMI : _zz_40__string = "IMI";
-      `Src2CtrlEnum_defaultEncoding_IMS : _zz_40__string = "IMS";
-      `Src2CtrlEnum_defaultEncoding_PC : _zz_40__string = "PC ";
-      default : _zz_40__string = "???";
-    endcase
-  end
-  always @(*) begin
-    case(execute_SRC1_CTRL)
-      `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS          ";
-      `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU         ";
-      `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT";
-      `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1        ";
-      default : execute_SRC1_CTRL_string = "????????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_42_)
-      `Src1CtrlEnum_defaultEncoding_RS : _zz_42__string = "RS          ";
-      `Src1CtrlEnum_defaultEncoding_IMU : _zz_42__string = "IMU         ";
-      `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_42__string = "PC_INCREMENT";
-      `Src1CtrlEnum_defaultEncoding_URS1 : _zz_42__string = "URS1        ";
-      default : _zz_42__string = "????????????";
-    endcase
-  end
-  always @(*) begin
-    case(execute_ALU_CTRL)
-      `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB ";
-      `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU";
-      `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE ";
-      default : execute_ALU_CTRL_string = "????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_45_)
-      `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_45__string = "ADD_SUB ";
-      `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_45__string = "SLT_SLTU";
-      `AluCtrlEnum_defaultEncoding_BITWISE : _zz_45__string = "BITWISE ";
-      default : _zz_45__string = "????????";
-    endcase
-  end
-  always @(*) begin
-    case(execute_ALU_BITWISE_CTRL)
-      `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1";
-      `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 ";
-      `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1";
-      default : execute_ALU_BITWISE_CTRL_string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_47_)
-      `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_47__string = "XOR_1";
-      `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_47__string = "OR_1 ";
-      `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_47__string = "AND_1";
-      default : _zz_47__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_55_)
-      `EnvCtrlEnum_defaultEncoding_NONE : _zz_55__string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : _zz_55__string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : _zz_55__string = "ECALL";
-      default : _zz_55__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_58_)
-      `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_58__string = "XOR_1";
-      `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_58__string = "OR_1 ";
-      `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_58__string = "AND_1";
-      default : _zz_58__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_59_)
-      `BranchCtrlEnum_defaultEncoding_INC : _zz_59__string = "INC ";
-      `BranchCtrlEnum_defaultEncoding_B : _zz_59__string = "B   ";
-      `BranchCtrlEnum_defaultEncoding_JAL : _zz_59__string = "JAL ";
-      `BranchCtrlEnum_defaultEncoding_JALR : _zz_59__string = "JALR";
-      default : _zz_59__string = "????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_60_)
-      `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_60__string = "ADD_SUB ";
-      `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_60__string = "SLT_SLTU";
-      `AluCtrlEnum_defaultEncoding_BITWISE : _zz_60__string = "BITWISE ";
-      default : _zz_60__string = "????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_62_)
-      `Src2CtrlEnum_defaultEncoding_RS : _zz_62__string = "RS ";
-      `Src2CtrlEnum_defaultEncoding_IMI : _zz_62__string = "IMI";
-      `Src2CtrlEnum_defaultEncoding_IMS : _zz_62__string = "IMS";
-      `Src2CtrlEnum_defaultEncoding_PC : _zz_62__string = "PC ";
-      default : _zz_62__string = "???";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_65_)
-      `Src1CtrlEnum_defaultEncoding_RS : _zz_65__string = "RS          ";
-      `Src1CtrlEnum_defaultEncoding_IMU : _zz_65__string = "IMU         ";
-      `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_65__string = "PC_INCREMENT";
-      `Src1CtrlEnum_defaultEncoding_URS1 : _zz_65__string = "URS1        ";
-      default : _zz_65__string = "????????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_70_)
-      `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_70__string = "DISABLE_1";
-      `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_70__string = "SLL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_70__string = "SRL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_70__string = "SRA_1    ";
-      default : _zz_70__string = "?????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_118_)
-      `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_118__string = "DISABLE_1";
-      `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_118__string = "SLL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_118__string = "SRL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_118__string = "SRA_1    ";
-      default : _zz_118__string = "?????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_119_)
-      `Src1CtrlEnum_defaultEncoding_RS : _zz_119__string = "RS          ";
-      `Src1CtrlEnum_defaultEncoding_IMU : _zz_119__string = "IMU         ";
-      `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_119__string = "PC_INCREMENT";
-      `Src1CtrlEnum_defaultEncoding_URS1 : _zz_119__string = "URS1        ";
-      default : _zz_119__string = "????????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_120_)
-      `Src2CtrlEnum_defaultEncoding_RS : _zz_120__string = "RS ";
-      `Src2CtrlEnum_defaultEncoding_IMI : _zz_120__string = "IMI";
-      `Src2CtrlEnum_defaultEncoding_IMS : _zz_120__string = "IMS";
-      `Src2CtrlEnum_defaultEncoding_PC : _zz_120__string = "PC ";
-      default : _zz_120__string = "???";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_121_)
-      `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_121__string = "ADD_SUB ";
-      `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_121__string = "SLT_SLTU";
-      `AluCtrlEnum_defaultEncoding_BITWISE : _zz_121__string = "BITWISE ";
-      default : _zz_121__string = "????????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_122_)
-      `BranchCtrlEnum_defaultEncoding_INC : _zz_122__string = "INC ";
-      `BranchCtrlEnum_defaultEncoding_B : _zz_122__string = "B   ";
-      `BranchCtrlEnum_defaultEncoding_JAL : _zz_122__string = "JAL ";
-      `BranchCtrlEnum_defaultEncoding_JALR : _zz_122__string = "JALR";
-      default : _zz_122__string = "????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_123_)
-      `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_123__string = "XOR_1";
-      `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_123__string = "OR_1 ";
-      `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_123__string = "AND_1";
-      default : _zz_123__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(_zz_124_)
-      `EnvCtrlEnum_defaultEncoding_NONE : _zz_124__string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : _zz_124__string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : _zz_124__string = "ECALL";
-      default : _zz_124__string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(decode_to_execute_ALU_BITWISE_CTRL)
-      `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
-      `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
-      `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
-      default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(decode_to_execute_SHIFT_CTRL)
-      `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
-      `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1    ";
-      `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1    ";
-      default : decode_to_execute_SHIFT_CTRL_string = "?????????";
-    endcase
-  end
-  always @(*) begin
-    case(decode_to_execute_ALU_CTRL)
-      `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
-      `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
-      `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE ";
-      default : decode_to_execute_ALU_CTRL_string = "????????";
-    endcase
-  end
-  always @(*) begin
-    case(decode_to_execute_BRANCH_CTRL)
-      `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC ";
-      `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B   ";
-      `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL ";
-      `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR";
-      default : decode_to_execute_BRANCH_CTRL_string = "????";
-    endcase
-  end
-  always @(*) begin
-    case(decode_to_execute_SRC1_CTRL)
-      `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS          ";
-      `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU         ";
-      `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
-      `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1        ";
-      default : decode_to_execute_SRC1_CTRL_string = "????????????";
-    endcase
-  end
-  always @(*) begin
-    case(decode_to_execute_ENV_CTRL)
-      `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL";
-      default : decode_to_execute_ENV_CTRL_string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(execute_to_memory_ENV_CTRL)
-      `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL";
-      default : execute_to_memory_ENV_CTRL_string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(memory_to_writeBack_ENV_CTRL)
-      `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE ";
-      `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET ";
-      `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL";
-      default : memory_to_writeBack_ENV_CTRL_string = "?????";
-    endcase
-  end
-  always @(*) begin
-    case(decode_to_execute_SRC2_CTRL)
-      `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS ";
-      `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI";
-      `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS";
-      `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC ";
-      default : decode_to_execute_SRC2_CTRL_string = "???";
-    endcase
-  end
-  `endif
-
-  assign decode_RS1 = _zz_52_;
-  assign execute_BRANCH_DO = _zz_33_;
-  assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE;
-  assign decode_BYPASSABLE_MEMORY_STAGE = _zz_54_;
-  assign decode_SRC2_FORCE_ZERO = _zz_44_;
-  assign decode_SRC2_CTRL = _zz_1_;
-  assign _zz_2_ = _zz_3_;
-  assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA;
-  assign execute_REGFILE_WRITE_DATA = _zz_46_;
-  assign decode_CSR_WRITE_OPCODE = _zz_29_;
-  assign execute_BRANCH_CALC = _zz_31_;
-  assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT;
-  assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT;
-  assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT;
-  assign decode_FORMAL_PC_NEXT = _zz_86_;
-  assign decode_SRC_LESS_UNSIGNED = _zz_63_;
-  assign decode_MEMORY_STORE = _zz_56_;
-  assign memory_MEMORY_READ_DATA = _zz_73_;
-  assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_53_;
-  assign decode_IS_CSR = _zz_64_;
-  assign decode_RS2 = _zz_51_;
-  assign _zz_4_ = _zz_5_;
-  assign _zz_6_ = _zz_7_;
-  assign decode_ENV_CTRL = _zz_8_;
-  assign _zz_9_ = _zz_10_;
-  assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW;
-  assign execute_MEMORY_ADDRESS_LOW = _zz_82_;
-  assign decode_SRC1_CTRL = _zz_11_;
-  assign _zz_12_ = _zz_13_;
-  assign decode_BRANCH_CTRL = _zz_14_;
-  assign _zz_15_ = _zz_16_;
-  assign decode_ALU_CTRL = _zz_17_;
-  assign _zz_18_ = _zz_19_;
-  assign decode_CSR_READ_OPCODE = _zz_28_;
-  assign decode_SHIFT_CTRL = _zz_20_;
-  assign _zz_21_ = _zz_22_;
-  assign decode_ALU_BITWISE_CTRL = _zz_23_;
-  assign _zz_24_ = _zz_25_;
-  assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE;
-  assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE;
-  assign execute_IS_CSR = decode_to_execute_IS_CSR;
-  assign memory_ENV_CTRL = _zz_26_;
-  assign execute_ENV_CTRL = _zz_27_;
-  assign writeBack_ENV_CTRL = _zz_30_;
-  assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC;
-  assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO;
-  assign execute_PC = decode_to_execute_PC;
-  assign execute_RS1 = decode_to_execute_RS1;
-  assign execute_BRANCH_CTRL = _zz_32_;
-  assign decode_RS2_USE = _zz_67_;
-  assign decode_RS1_USE = _zz_61_;
-  assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID;
-  assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
-  assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID;
-  assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION;
-  assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE;
-  assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID;
-  always @ (*) begin
-    _zz_34_ = execute_REGFILE_WRITE_DATA;
-    if(_zz_164_)begin
-      _zz_34_ = _zz_133_;
-    end
-    if(_zz_165_)begin
-      _zz_34_ = execute_CsrPlugin_readData;
-    end
-  end
-
-  assign execute_SHIFT_CTRL = _zz_35_;
-  assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED;
-  assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO;
-  assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS;
-  assign _zz_39_ = execute_PC;
-  assign execute_SRC2_CTRL = _zz_40_;
-  assign execute_SRC1_CTRL = _zz_42_;
-  assign decode_SRC_USE_SUB_LESS = _zz_68_;
-  assign decode_SRC_ADD_ZERO = _zz_57_;
-  assign execute_SRC_ADD_SUB = _zz_38_;
-  assign execute_SRC_LESS = _zz_36_;
-  assign execute_ALU_CTRL = _zz_45_;
-  assign execute_SRC2 = _zz_41_;
-  assign execute_SRC1 = _zz_43_;
-  assign execute_ALU_BITWISE_CTRL = _zz_47_;
-  assign _zz_48_ = writeBack_INSTRUCTION;
-  assign _zz_49_ = writeBack_REGFILE_WRITE_VALID;
-  always @ (*) begin
-    _zz_50_ = 1'b0;
-    if(lastStageRegFileWrite_valid)begin
-      _zz_50_ = 1'b1;
-    end
-  end
-
-  assign decode_INSTRUCTION_ANTICIPATED = _zz_89_;
-  always @ (*) begin
-    decode_REGFILE_WRITE_VALID = _zz_69_;
-    if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin
-      decode_REGFILE_WRITE_VALID = 1'b0;
-    end
-  end
-
-  assign decode_LEGAL_INSTRUCTION = _zz_71_;
-  assign decode_INSTRUCTION_READY = 1'b1;
-  assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE;
-  always @ (*) begin
-    _zz_72_ = writeBack_REGFILE_WRITE_DATA;
-    if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin
-      _zz_72_ = writeBack_DBusSimplePlugin_rspFormated;
-    end
-  end
-
-  assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE;
-  assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW;
-  assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA;
-  assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT;
-  assign memory_MMU_RSP_physicalAddress = execute_to_memory_MMU_RSP_physicalAddress;
-  assign memory_MMU_RSP_isIoAccess = execute_to_memory_MMU_RSP_isIoAccess;
-  assign memory_MMU_RSP_allowRead = execute_to_memory_MMU_RSP_allowRead;
-  assign memory_MMU_RSP_allowWrite = execute_to_memory_MMU_RSP_allowWrite;
-  assign memory_MMU_RSP_allowExecute = execute_to_memory_MMU_RSP_allowExecute;
-  assign memory_MMU_RSP_exception = execute_to_memory_MMU_RSP_exception;
-  assign memory_MMU_RSP_refilling = execute_to_memory_MMU_RSP_refilling;
-  assign memory_PC = execute_to_memory_PC;
-  assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT;
-  assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA;
-  assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE;
-  assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE;
-  assign execute_MMU_FAULT = _zz_81_;
-  assign execute_MMU_RSP_physicalAddress = _zz_74_;
-  assign execute_MMU_RSP_isIoAccess = _zz_75_;
-  assign execute_MMU_RSP_allowRead = _zz_76_;
-  assign execute_MMU_RSP_allowWrite = _zz_77_;
-  assign execute_MMU_RSP_allowExecute = _zz_78_;
-  assign execute_MMU_RSP_exception = _zz_79_;
-  assign execute_MMU_RSP_refilling = _zz_80_;
-  assign execute_SRC_ADD = _zz_37_;
-  assign execute_RS2 = decode_to_execute_RS2;
-  assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION;
-  assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE;
-  assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE;
-  assign execute_ALIGNEMENT_FAULT = _zz_83_;
-  assign decode_MEMORY_ENABLE = _zz_66_;
-  always @ (*) begin
-    _zz_84_ = memory_FORMAL_PC_NEXT;
-    if(DBusSimplePlugin_redoBranch_valid)begin
-      _zz_84_ = DBusSimplePlugin_redoBranch_payload;
-    end
-    if(BranchPlugin_jumpInterface_valid)begin
-      _zz_84_ = BranchPlugin_jumpInterface_payload;
-    end
-  end
-
-  always @ (*) begin
-    _zz_85_ = decode_FORMAL_PC_NEXT;
-    if(IBusSimplePlugin_redoBranch_valid)begin
-      _zz_85_ = IBusSimplePlugin_redoBranch_payload;
-    end
-  end
-
-  assign decode_PC = _zz_88_;
-  assign decode_INSTRUCTION = _zz_87_;
-  assign writeBack_PC = memory_to_writeBack_PC;
-  assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION;
-  always @ (*) begin
-    decode_arbitration_haltItself = 1'b0;
-    if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin
-      decode_arbitration_haltItself = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    decode_arbitration_haltByOther = 1'b0;
-    if((decode_arbitration_isValid && (_zz_134_ || _zz_135_)))begin
-      decode_arbitration_haltByOther = 1'b1;
-    end
-    if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin
-      decode_arbitration_haltByOther = decode_arbitration_isValid;
-    end
-    if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin
-      decode_arbitration_haltByOther = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    decode_arbitration_removeIt = 1'b0;
-    if(_zz_166_)begin
-      decode_arbitration_removeIt = 1'b1;
-    end
-    if(decode_arbitration_isFlushed)begin
-      decode_arbitration_removeIt = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    decode_arbitration_flushIt = 1'b0;
-    if(IBusSimplePlugin_redoBranch_valid)begin
-      decode_arbitration_flushIt = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    decode_arbitration_flushNext = 1'b0;
-    if(IBusSimplePlugin_redoBranch_valid)begin
-      decode_arbitration_flushNext = 1'b1;
-    end
-    if(_zz_166_)begin
-      decode_arbitration_flushNext = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    execute_arbitration_haltItself = 1'b0;
-    if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_106_)))begin
-      execute_arbitration_haltItself = 1'b1;
-    end
-    if(_zz_164_)begin
-      if(_zz_167_)begin
-        if(! execute_LightShifterPlugin_done) begin
-          execute_arbitration_haltItself = 1'b1;
-        end
-      end
-    end
-    if(_zz_165_)begin
-      if(execute_CsrPlugin_blockedBySideEffects)begin
-        execute_arbitration_haltItself = 1'b1;
-      end
-    end
-  end
-
-  assign execute_arbitration_haltByOther = 1'b0;
-  always @ (*) begin
-    execute_arbitration_removeIt = 1'b0;
-    if(CsrPlugin_selfException_valid)begin
-      execute_arbitration_removeIt = 1'b1;
-    end
-    if(execute_arbitration_isFlushed)begin
-      execute_arbitration_removeIt = 1'b1;
-    end
-  end
-
-  assign execute_arbitration_flushIt = 1'b0;
-  always @ (*) begin
-    execute_arbitration_flushNext = 1'b0;
-    if(CsrPlugin_selfException_valid)begin
-      execute_arbitration_flushNext = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    memory_arbitration_haltItself = 1'b0;
-    if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin
-      memory_arbitration_haltItself = 1'b1;
-    end
-  end
-
-  assign memory_arbitration_haltByOther = 1'b0;
-  always @ (*) begin
-    memory_arbitration_removeIt = 1'b0;
-    if(_zz_168_)begin
-      memory_arbitration_removeIt = 1'b1;
-    end
-    if(memory_arbitration_isFlushed)begin
-      memory_arbitration_removeIt = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    memory_arbitration_flushIt = 1'b0;
-    if(DBusSimplePlugin_redoBranch_valid)begin
-      memory_arbitration_flushIt = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    memory_arbitration_flushNext = 1'b0;
-    if(DBusSimplePlugin_redoBranch_valid)begin
-      memory_arbitration_flushNext = 1'b1;
-    end
-    if(BranchPlugin_jumpInterface_valid)begin
-      memory_arbitration_flushNext = 1'b1;
-    end
-    if(_zz_168_)begin
-      memory_arbitration_flushNext = 1'b1;
-    end
-  end
-
-  assign writeBack_arbitration_haltItself = 1'b0;
-  assign writeBack_arbitration_haltByOther = 1'b0;
-  always @ (*) begin
-    writeBack_arbitration_removeIt = 1'b0;
-    if(writeBack_arbitration_isFlushed)begin
-      writeBack_arbitration_removeIt = 1'b1;
-    end
-  end
-
-  assign writeBack_arbitration_flushIt = 1'b0;
-  always @ (*) begin
-    writeBack_arbitration_flushNext = 1'b0;
-    if(_zz_169_)begin
-      writeBack_arbitration_flushNext = 1'b1;
-    end
-    if(_zz_170_)begin
-      writeBack_arbitration_flushNext = 1'b1;
-    end
-  end
-
-  assign lastStageInstruction = writeBack_INSTRUCTION;
-  assign lastStagePc = writeBack_PC;
-  assign lastStageIsValid = writeBack_arbitration_isValid;
-  assign lastStageIsFiring = writeBack_arbitration_isFiring;
-  always @ (*) begin
-    IBusSimplePlugin_fetcherHalt = 1'b0;
-    if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != (4'b0000)))begin
-      IBusSimplePlugin_fetcherHalt = 1'b1;
-    end
-    if(_zz_169_)begin
-      IBusSimplePlugin_fetcherHalt = 1'b1;
-    end
-    if(_zz_170_)begin
-      IBusSimplePlugin_fetcherHalt = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    IBusSimplePlugin_fetcherflushIt = 1'b0;
-    if(({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)))begin
-      IBusSimplePlugin_fetcherflushIt = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    IBusSimplePlugin_incomingInstruction = 1'b0;
-    if(IBusSimplePlugin_iBusRsp_stages_1_input_valid)begin
-      IBusSimplePlugin_incomingInstruction = 1'b1;
-    end
-    if(IBusSimplePlugin_injector_decodeInput_valid)begin
-      IBusSimplePlugin_incomingInstruction = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    CsrPlugin_jumpInterface_valid = 1'b0;
-    if(_zz_169_)begin
-      CsrPlugin_jumpInterface_valid = 1'b1;
-    end
-    if(_zz_170_)begin
-      CsrPlugin_jumpInterface_valid = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
-    if(_zz_169_)begin
-      CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)};
-    end
-    if(_zz_170_)begin
-      case(_zz_171_)
-        2'b11 : begin
-          CsrPlugin_jumpInterface_payload = CsrPlugin_mepc;
-        end
-        default : begin
-        end
-      endcase
-    end
-  end
-
-  assign CsrPlugin_forceMachineWire = 1'b0;
-  assign CsrPlugin_allowInterrupts = 1'b1;
-  assign CsrPlugin_allowException = 1'b1;
-  assign IBusSimplePlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,IBusSimplePlugin_redoBranch_valid}}} != (4'b0000));
-  assign _zz_90_ = {IBusSimplePlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}};
-  assign _zz_91_ = (_zz_90_ & (~ _zz_190_));
-  assign _zz_92_ = _zz_91_[3];
-  assign _zz_93_ = (_zz_91_[1] || _zz_92_);
-  assign _zz_94_ = (_zz_91_[2] || _zz_92_);
-  assign IBusSimplePlugin_jump_pcLoad_payload = _zz_163_;
-  always @ (*) begin
-    IBusSimplePlugin_fetchPc_corrected = 1'b0;
-    if(IBusSimplePlugin_jump_pcLoad_valid)begin
-      IBusSimplePlugin_fetchPc_corrected = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b0;
-    if(IBusSimplePlugin_iBusRsp_stages_1_input_ready)begin
-      IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_192_);
-    if(IBusSimplePlugin_jump_pcLoad_valid)begin
-      IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_jump_pcLoad_payload;
-    end
-    IBusSimplePlugin_fetchPc_pc[0] = 1'b0;
-    IBusSimplePlugin_fetchPc_pc[1] = 1'b0;
-  end
-
-  assign IBusSimplePlugin_fetchPc_output_valid = ((! IBusSimplePlugin_fetcherHalt) && IBusSimplePlugin_fetchPc_booted);
-  assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_pc;
-  always @ (*) begin
-    IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid;
-    if(IBusSimplePlugin_mmuBus_busy)begin
-      IBusSimplePlugin_iBusRsp_stages_0_input_valid = 1'b0;
-    end
-  end
-
-  assign IBusSimplePlugin_fetchPc_output_ready = IBusSimplePlugin_iBusRsp_stages_0_input_ready;
-  assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = IBusSimplePlugin_fetchPc_output_payload;
-  assign IBusSimplePlugin_iBusRsp_stages_0_inputSample = 1'b1;
-  always @ (*) begin
-    IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0;
-    if((IBusSimplePlugin_iBusRsp_stages_0_input_valid && ((! IBusSimplePlugin_cmd_valid) || (! IBusSimplePlugin_cmd_ready))))begin
-      IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1;
-    end
-    if(_zz_172_)begin
-      IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0;
-    end
-  end
-
-  assign _zz_95_ = (! IBusSimplePlugin_iBusRsp_stages_0_halt);
-  always @ (*) begin
-    IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_95_);
-    if(IBusSimplePlugin_mmuBus_busy)begin
-      IBusSimplePlugin_iBusRsp_stages_0_input_ready = 1'b0;
-    end
-  end
-
-  assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_95_);
-  assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = IBusSimplePlugin_iBusRsp_stages_0_input_payload;
-  assign IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b0;
-  assign _zz_96_ = (! IBusSimplePlugin_iBusRsp_stages_1_halt);
-  assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_96_);
-  assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_96_);
-  assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload;
-  assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_97_;
-  assign _zz_97_ = ((1'b0 && (! _zz_98_)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready);
-  assign _zz_98_ = _zz_99_;
-  assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_98_;
-  assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = IBusSimplePlugin_fetchPc_pcReg;
-  always @ (*) begin
-    IBusSimplePlugin_iBusRsp_readyForError = 1'b1;
-    if(IBusSimplePlugin_injector_decodeInput_valid)begin
-      IBusSimplePlugin_iBusRsp_readyForError = 1'b0;
-    end
-    if((! IBusSimplePlugin_pcValids_0))begin
-      IBusSimplePlugin_iBusRsp_readyForError = 1'b0;
-    end
-  end
-
-  assign IBusSimplePlugin_iBusRsp_inputBeforeStage_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready);
-  assign IBusSimplePlugin_injector_decodeInput_valid = _zz_100_;
-  assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_101_;
-  assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_102_;
-  assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_103_;
-  assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_104_;
-  assign _zz_89_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst);
-  assign IBusSimplePlugin_pcValids_0 = IBusSimplePlugin_injector_nextPcCalc_valids_1;
-  assign IBusSimplePlugin_pcValids_1 = IBusSimplePlugin_injector_nextPcCalc_valids_2;
-  assign IBusSimplePlugin_pcValids_2 = IBusSimplePlugin_injector_nextPcCalc_valids_3;
-  assign IBusSimplePlugin_pcValids_3 = IBusSimplePlugin_injector_nextPcCalc_valids_4;
-  assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck);
-  assign decode_arbitration_isValid = (IBusSimplePlugin_injector_decodeInput_valid && (! IBusSimplePlugin_injector_decodeRemoved));
-  assign _zz_88_ = IBusSimplePlugin_injector_decodeInput_payload_pc;
-  assign _zz_87_ = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst;
-  assign _zz_86_ = (decode_PC + (32'b00000000000000000000000000000100));
-  assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid;
-  assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready;
-  assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc;
-  assign IBusSimplePlugin_pendingCmdNext = (_zz_193_ - _zz_197_);
-  always @ (*) begin
-    IBusSimplePlugin_cmd_valid = ((IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) && (IBusSimplePlugin_pendingCmd != (3'b111)));
-    if(_zz_172_)begin
-      IBusSimplePlugin_cmd_valid = 1'b0;
-    end
-  end
-
-  assign IBusSimplePlugin_mmuBus_cmd_isValid = IBusSimplePlugin_iBusRsp_stages_0_input_valid;
-  assign IBusSimplePlugin_mmuBus_cmd_virtualAddress = IBusSimplePlugin_iBusRsp_stages_0_input_payload;
-  assign IBusSimplePlugin_mmuBus_cmd_bypassTranslation = 1'b0;
-  assign IBusSimplePlugin_mmuBus_end = ((IBusSimplePlugin_iBusRsp_stages_0_output_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) || IBusSimplePlugin_fetcherflushIt);
-  assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_mmuBus_rsp_physicalAddress[31 : 2],(2'b00)};
-  assign iBus_rsp_takeWhen_valid = (iBus_rsp_valid && (! (IBusSimplePlugin_rspJoin_discardCounter != (3'b000))));
-  assign iBus_rsp_takeWhen_payload_error = iBus_rsp_payload_error;
-  assign iBus_rsp_takeWhen_payload_inst = iBus_rsp_payload_inst;
-  assign IBusSimplePlugin_rspJoin_rspBufferOutput_valid = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid;
-  assign IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error;
-  assign IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst;
-  assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_1_output_payload;
-  always @ (*) begin
-    IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error;
-    if((! IBusSimplePlugin_rspJoin_rspBufferOutput_valid))begin
-      IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = 1'b0;
-    end
-  end
-
-  assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst;
-  always @ (*) begin
-    IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0;
-    if(_zz_173_)begin
-      IBusSimplePlugin_rspJoin_exceptionDetected = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    IBusSimplePlugin_rspJoin_redoRequired = 1'b0;
-    if((IBusSimplePlugin_iBusRsp_stages_1_input_valid && IBusSimplePlugin_mmu_joinCtx_refilling))begin
-      IBusSimplePlugin_rspJoin_redoRequired = 1'b1;
-    end
-  end
-
-  assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_1_output_valid && IBusSimplePlugin_rspJoin_rspBufferOutput_valid);
-  assign IBusSimplePlugin_rspJoin_join_payload_pc = IBusSimplePlugin_rspJoin_fetchRsp_pc;
-  assign IBusSimplePlugin_rspJoin_join_payload_rsp_error = IBusSimplePlugin_rspJoin_fetchRsp_rsp_error;
-  assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst;
-  assign IBusSimplePlugin_rspJoin_join_payload_isRvc = IBusSimplePlugin_rspJoin_fetchRsp_isRvc;
-  assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_valid ? (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready) : IBusSimplePlugin_rspJoin_join_ready);
-  assign IBusSimplePlugin_rspJoin_rspBufferOutput_ready = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready);
-  assign _zz_105_ = (! (IBusSimplePlugin_rspJoin_exceptionDetected || IBusSimplePlugin_rspJoin_redoRequired));
-  assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_inputBeforeStage_ready && _zz_105_);
-  assign IBusSimplePlugin_iBusRsp_inputBeforeStage_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_105_);
-  assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc;
-  assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error;
-  assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst;
-  assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc;
-  assign IBusSimplePlugin_redoBranch_valid = (IBusSimplePlugin_rspJoin_redoRequired && IBusSimplePlugin_iBusRsp_readyForError);
-  assign IBusSimplePlugin_redoBranch_payload = decode_PC;
-  always @ (*) begin
-    IBusSimplePlugin_decodeExceptionPort_payload_code = (4'bxxxx);
-    if(_zz_173_)begin
-      IBusSimplePlugin_decodeExceptionPort_payload_code = (4'b1100);
-    end
-  end
-
-  assign IBusSimplePlugin_decodeExceptionPort_payload_badAddr = {IBusSimplePlugin_rspJoin_join_payload_pc[31 : 2],(2'b00)};
-  assign IBusSimplePlugin_decodeExceptionPort_valid = (IBusSimplePlugin_rspJoin_exceptionDetected && IBusSimplePlugin_iBusRsp_readyForError);
-  assign _zz_106_ = 1'b0;
-  assign _zz_83_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0))));
-  always @ (*) begin
-    execute_DBusSimplePlugin_skipCmd = 1'b0;
-    if(execute_ALIGNEMENT_FAULT)begin
-      execute_DBusSimplePlugin_skipCmd = 1'b1;
-    end
-    if((execute_MMU_FAULT || execute_MMU_RSP_refilling))begin
-      execute_DBusSimplePlugin_skipCmd = 1'b1;
-    end
-  end
-
-  assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_106_));
-  assign dBus_cmd_payload_wr = execute_MEMORY_STORE;
-  assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12];
-  always @ (*) begin
-    case(dBus_cmd_payload_size)
-      2'b00 : begin
-        _zz_107_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]};
-      end
-      2'b01 : begin
-        _zz_107_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]};
-      end
-      default : begin
-        _zz_107_ = execute_RS2[31 : 0];
-      end
-    endcase
-  end
-
-  assign dBus_cmd_payload_data = _zz_107_;
-  assign _zz_82_ = dBus_cmd_payload_address[1 : 0];
-  always @ (*) begin
-    case(dBus_cmd_payload_size)
-      2'b00 : begin
-        _zz_108_ = (4'b0001);
-      end
-      2'b01 : begin
-        _zz_108_ = (4'b0011);
-      end
-      default : begin
-        _zz_108_ = (4'b1111);
-      end
-    endcase
-  end
-
-  assign execute_DBusSimplePlugin_formalMask = (_zz_108_ <<< dBus_cmd_payload_address[1 : 0]);
-  assign DBusSimplePlugin_mmuBus_cmd_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE);
-  assign DBusSimplePlugin_mmuBus_cmd_virtualAddress = execute_SRC_ADD;
-  assign DBusSimplePlugin_mmuBus_cmd_bypassTranslation = 1'b0;
-  assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt);
-  assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress;
-  assign _zz_81_ = ((execute_MMU_RSP_exception || ((! execute_MMU_RSP_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP_allowRead) && (! execute_MEMORY_STORE)));
-  assign _zz_74_ = DBusSimplePlugin_mmuBus_rsp_physicalAddress;
-  assign _zz_75_ = DBusSimplePlugin_mmuBus_rsp_isIoAccess;
-  assign _zz_76_ = DBusSimplePlugin_mmuBus_rsp_allowRead;
-  assign _zz_77_ = DBusSimplePlugin_mmuBus_rsp_allowWrite;
-  assign _zz_78_ = DBusSimplePlugin_mmuBus_rsp_allowExecute;
-  assign _zz_79_ = DBusSimplePlugin_mmuBus_rsp_exception;
-  assign _zz_80_ = DBusSimplePlugin_mmuBus_rsp_refilling;
-  assign _zz_73_ = dBus_rsp_data;
-  always @ (*) begin
-    DBusSimplePlugin_memoryExceptionPort_valid = 1'b0;
-    if(_zz_174_)begin
-      DBusSimplePlugin_memoryExceptionPort_valid = 1'b1;
-    end
-    if(memory_ALIGNEMENT_FAULT)begin
-      DBusSimplePlugin_memoryExceptionPort_valid = 1'b1;
-    end
-    if(memory_MMU_RSP_refilling)begin
-      DBusSimplePlugin_memoryExceptionPort_valid = 1'b0;
-    end else begin
-      if(memory_MMU_FAULT)begin
-        DBusSimplePlugin_memoryExceptionPort_valid = 1'b1;
-      end
-    end
-    if(_zz_175_)begin
-      DBusSimplePlugin_memoryExceptionPort_valid = 1'b0;
-    end
-  end
-
-  always @ (*) begin
-    DBusSimplePlugin_memoryExceptionPort_payload_code = (4'bxxxx);
-    if(_zz_174_)begin
-      DBusSimplePlugin_memoryExceptionPort_payload_code = (4'b0101);
-    end
-    if(memory_ALIGNEMENT_FAULT)begin
-      DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_202_};
-    end
-    if(! memory_MMU_RSP_refilling) begin
-      if(memory_MMU_FAULT)begin
-        DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? (4'b1111) : (4'b1101));
-      end
-    end
-  end
-
-  assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA;
-  always @ (*) begin
-    DBusSimplePlugin_redoBranch_valid = 1'b0;
-    if(memory_MMU_RSP_refilling)begin
-      DBusSimplePlugin_redoBranch_valid = 1'b1;
-    end
-    if(_zz_175_)begin
-      DBusSimplePlugin_redoBranch_valid = 1'b0;
-    end
-  end
-
-  assign DBusSimplePlugin_redoBranch_payload = memory_PC;
-  always @ (*) begin
-    writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA;
-    case(writeBack_MEMORY_ADDRESS_LOW)
-      2'b01 : begin
-        writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8];
-      end
-      2'b10 : begin
-        writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16];
-      end
-      2'b11 : begin
-        writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24];
-      end
-      default : begin
-      end
-    endcase
-  end
-
-  assign _zz_109_ = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14]));
-  always @ (*) begin
-    _zz_110_[31] = _zz_109_;
-    _zz_110_[30] = _zz_109_;
-    _zz_110_[29] = _zz_109_;
-    _zz_110_[28] = _zz_109_;
-    _zz_110_[27] = _zz_109_;
-    _zz_110_[26] = _zz_109_;
-    _zz_110_[25] = _zz_109_;
-    _zz_110_[24] = _zz_109_;
-    _zz_110_[23] = _zz_109_;
-    _zz_110_[22] = _zz_109_;
-    _zz_110_[21] = _zz_109_;
-    _zz_110_[20] = _zz_109_;
-    _zz_110_[19] = _zz_109_;
-    _zz_110_[18] = _zz_109_;
-    _zz_110_[17] = _zz_109_;
-    _zz_110_[16] = _zz_109_;
-    _zz_110_[15] = _zz_109_;
-    _zz_110_[14] = _zz_109_;
-    _zz_110_[13] = _zz_109_;
-    _zz_110_[12] = _zz_109_;
-    _zz_110_[11] = _zz_109_;
-    _zz_110_[10] = _zz_109_;
-    _zz_110_[9] = _zz_109_;
-    _zz_110_[8] = _zz_109_;
-    _zz_110_[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0];
-  end
-
-  assign _zz_111_ = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14]));
-  always @ (*) begin
-    _zz_112_[31] = _zz_111_;
-    _zz_112_[30] = _zz_111_;
-    _zz_112_[29] = _zz_111_;
-    _zz_112_[28] = _zz_111_;
-    _zz_112_[27] = _zz_111_;
-    _zz_112_[26] = _zz_111_;
-    _zz_112_[25] = _zz_111_;
-    _zz_112_[24] = _zz_111_;
-    _zz_112_[23] = _zz_111_;
-    _zz_112_[22] = _zz_111_;
-    _zz_112_[21] = _zz_111_;
-    _zz_112_[20] = _zz_111_;
-    _zz_112_[19] = _zz_111_;
-    _zz_112_[18] = _zz_111_;
-    _zz_112_[17] = _zz_111_;
-    _zz_112_[16] = _zz_111_;
-    _zz_112_[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0];
-  end
-
-  always @ (*) begin
-    case(_zz_188_)
-      2'b00 : begin
-        writeBack_DBusSimplePlugin_rspFormated = _zz_110_;
-      end
-      2'b01 : begin
-        writeBack_DBusSimplePlugin_rspFormated = _zz_112_;
-      end
-      default : begin
-        writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted;
-      end
-    endcase
-  end
-
-  assign IBusSimplePlugin_mmuBus_rsp_physicalAddress = IBusSimplePlugin_mmuBus_cmd_virtualAddress;
-  assign IBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1;
-  assign IBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1;
-  assign IBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1;
-  assign IBusSimplePlugin_mmuBus_rsp_isIoAccess = IBusSimplePlugin_mmuBus_rsp_physicalAddress[31];
-  assign IBusSimplePlugin_mmuBus_rsp_exception = 1'b0;
-  assign IBusSimplePlugin_mmuBus_rsp_refilling = 1'b0;
-  assign IBusSimplePlugin_mmuBus_busy = 1'b0;
-  assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_virtualAddress;
-  assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1;
-  assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1;
-  assign DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1;
-  assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = DBusSimplePlugin_mmuBus_rsp_physicalAddress[31];
-  assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0;
-  assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0;
-  assign DBusSimplePlugin_mmuBus_busy = 1'b0;
-  assign _zz_114_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000010000));
-  assign _zz_115_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000));
-  assign _zz_116_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000));
-  assign _zz_117_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100));
-  assign _zz_113_ = {(_zz_114_ != (1'b0)),{(((decode_INSTRUCTION & _zz_245_) == (32'b00000000000000000000000000010000)) != (1'b0)),{((_zz_246_ == _zz_247_) != (1'b0)),{(_zz_248_ != (1'b0)),{(_zz_249_ != _zz_250_),{_zz_251_,{_zz_252_,_zz_253_}}}}}}};
-  assign _zz_71_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_345_) == (32'b00000000000000000001000001110011)),{(_zz_346_ == _zz_347_),{_zz_348_,{_zz_349_,_zz_350_}}}}}}} != (20'b00000000000000000000));
-  assign _zz_118_ = _zz_113_[1 : 0];
-  assign _zz_70_ = _zz_118_;
-  assign _zz_69_ = _zz_203_[0];
-  assign _zz_68_ = _zz_204_[0];
-  assign _zz_67_ = _zz_205_[0];
-  assign _zz_66_ = _zz_206_[0];
-  assign _zz_119_ = _zz_113_[8 : 7];
-  assign _zz_65_ = _zz_119_;
-  assign _zz_64_ = _zz_207_[0];
-  assign _zz_63_ = _zz_208_[0];
-  assign _zz_120_ = _zz_113_[12 : 11];
-  assign _zz_62_ = _zz_120_;
-  assign _zz_61_ = _zz_209_[0];
-  assign _zz_121_ = _zz_113_[15 : 14];
-  assign _zz_60_ = _zz_121_;
-  assign _zz_122_ = _zz_113_[17 : 16];
-  assign _zz_59_ = _zz_122_;
-  assign _zz_123_ = _zz_113_[19 : 18];
-  assign _zz_58_ = _zz_123_;
-  assign _zz_57_ = _zz_210_[0];
-  assign _zz_56_ = _zz_211_[0];
-  assign _zz_124_ = _zz_113_[23 : 22];
-  assign _zz_55_ = _zz_124_;
-  assign _zz_54_ = _zz_212_[0];
-  assign _zz_53_ = _zz_213_[0];
-  assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION));
-  assign decodeExceptionPort_payload_code = (4'b0010);
-  assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION;
-  assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15];
-  assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20];
-  assign decode_RegFilePlugin_rs1Data = _zz_161_;
-  assign decode_RegFilePlugin_rs2Data = _zz_162_;
-  assign _zz_52_ = decode_RegFilePlugin_rs1Data;
-  assign _zz_51_ = decode_RegFilePlugin_rs2Data;
-  always @ (*) begin
-    lastStageRegFileWrite_valid = (_zz_49_ && writeBack_arbitration_isFiring);
-    if(_zz_125_)begin
-      lastStageRegFileWrite_valid = 1'b1;
-    end
-  end
-
-  assign lastStageRegFileWrite_payload_address = _zz_48_[11 : 7];
-  assign lastStageRegFileWrite_payload_data = _zz_72_;
-  always @ (*) begin
-    case(execute_ALU_BITWISE_CTRL)
-      `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin
-        execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2);
-      end
-      `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin
-        execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2);
-      end
-      default : begin
-        execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2);
-      end
-    endcase
-  end
-
-  always @ (*) begin
-    case(execute_ALU_CTRL)
-      `AluCtrlEnum_defaultEncoding_BITWISE : begin
-        _zz_126_ = execute_IntAluPlugin_bitwise;
-      end
-      `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin
-        _zz_126_ = {31'd0, _zz_214_};
-      end
-      default : begin
-        _zz_126_ = execute_SRC_ADD_SUB;
-      end
-    endcase
-  end
-
-  assign _zz_46_ = _zz_126_;
-  assign _zz_44_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS));
-  always @ (*) begin
-    case(execute_SRC1_CTRL)
-      `Src1CtrlEnum_defaultEncoding_RS : begin
-        _zz_127_ = execute_RS1;
-      end
-      `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin
-        _zz_127_ = {29'd0, _zz_215_};
-      end
-      `Src1CtrlEnum_defaultEncoding_IMU : begin
-        _zz_127_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)};
-      end
-      default : begin
-        _zz_127_ = {27'd0, _zz_216_};
-      end
-    endcase
-  end
-
-  assign _zz_43_ = _zz_127_;
-  assign _zz_128_ = _zz_217_[11];
-  always @ (*) begin
-    _zz_129_[19] = _zz_128_;
-    _zz_129_[18] = _zz_128_;
-    _zz_129_[17] = _zz_128_;
-    _zz_129_[16] = _zz_128_;
-    _zz_129_[15] = _zz_128_;
-    _zz_129_[14] = _zz_128_;
-    _zz_129_[13] = _zz_128_;
-    _zz_129_[12] = _zz_128_;
-    _zz_129_[11] = _zz_128_;
-    _zz_129_[10] = _zz_128_;
-    _zz_129_[9] = _zz_128_;
-    _zz_129_[8] = _zz_128_;
-    _zz_129_[7] = _zz_128_;
-    _zz_129_[6] = _zz_128_;
-    _zz_129_[5] = _zz_128_;
-    _zz_129_[4] = _zz_128_;
-    _zz_129_[3] = _zz_128_;
-    _zz_129_[2] = _zz_128_;
-    _zz_129_[1] = _zz_128_;
-    _zz_129_[0] = _zz_128_;
-  end
-
-  assign _zz_130_ = _zz_218_[11];
-  always @ (*) begin
-    _zz_131_[19] = _zz_130_;
-    _zz_131_[18] = _zz_130_;
-    _zz_131_[17] = _zz_130_;
-    _zz_131_[16] = _zz_130_;
-    _zz_131_[15] = _zz_130_;
-    _zz_131_[14] = _zz_130_;
-    _zz_131_[13] = _zz_130_;
-    _zz_131_[12] = _zz_130_;
-    _zz_131_[11] = _zz_130_;
-    _zz_131_[10] = _zz_130_;
-    _zz_131_[9] = _zz_130_;
-    _zz_131_[8] = _zz_130_;
-    _zz_131_[7] = _zz_130_;
-    _zz_131_[6] = _zz_130_;
-    _zz_131_[5] = _zz_130_;
-    _zz_131_[4] = _zz_130_;
-    _zz_131_[3] = _zz_130_;
-    _zz_131_[2] = _zz_130_;
-    _zz_131_[1] = _zz_130_;
-    _zz_131_[0] = _zz_130_;
-  end
-
-  always @ (*) begin
-    case(execute_SRC2_CTRL)
-      `Src2CtrlEnum_defaultEncoding_RS : begin
-        _zz_132_ = execute_RS2;
-      end
-      `Src2CtrlEnum_defaultEncoding_IMI : begin
-        _zz_132_ = {_zz_129_,execute_INSTRUCTION[31 : 20]};
-      end
-      `Src2CtrlEnum_defaultEncoding_IMS : begin
-        _zz_132_ = {_zz_131_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}};
-      end
-      default : begin
-        _zz_132_ = _zz_39_;
-      end
-    endcase
-  end
-
-  assign _zz_41_ = _zz_132_;
-  always @ (*) begin
-    execute_SrcPlugin_addSub = _zz_219_;
-    if(execute_SRC2_FORCE_ZERO)begin
-      execute_SrcPlugin_addSub = execute_SRC1;
-    end
-  end
-
-  assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31]));
-  assign _zz_38_ = execute_SrcPlugin_addSub;
-  assign _zz_37_ = execute_SrcPlugin_addSub;
-  assign _zz_36_ = execute_SrcPlugin_less;
-  assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1);
-  assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]);
-  assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1);
-  assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000));
-  always @ (*) begin
-    case(execute_SHIFT_CTRL)
-      `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin
-        _zz_133_ = (execute_LightShifterPlugin_shiftInput <<< 1);
-      end
-      default : begin
-        _zz_133_ = _zz_226_;
-      end
-    endcase
-  end
-
-  always @ (*) begin
-    _zz_134_ = 1'b0;
-    if(_zz_137_)begin
-      if((_zz_138_ == decode_INSTRUCTION[19 : 15]))begin
-        _zz_134_ = 1'b1;
-      end
-    end
-    if(_zz_176_)begin
-      if(_zz_177_)begin
-        if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin
-          _zz_134_ = 1'b1;
-        end
-      end
-    end
-    if(_zz_178_)begin
-      if(_zz_179_)begin
-        if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin
-          _zz_134_ = 1'b1;
-        end
-      end
-    end
-    if(_zz_180_)begin
-      if(_zz_181_)begin
-        if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin
-          _zz_134_ = 1'b1;
-        end
-      end
-    end
-    if((! decode_RS1_USE))begin
-      _zz_134_ = 1'b0;
-    end
-  end
-
-  always @ (*) begin
-    _zz_135_ = 1'b0;
-    if(_zz_137_)begin
-      if((_zz_138_ == decode_INSTRUCTION[24 : 20]))begin
-        _zz_135_ = 1'b1;
-      end
-    end
-    if(_zz_176_)begin
-      if(_zz_177_)begin
-        if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin
-          _zz_135_ = 1'b1;
-        end
-      end
-    end
-    if(_zz_178_)begin
-      if(_zz_179_)begin
-        if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin
-          _zz_135_ = 1'b1;
-        end
-      end
-    end
-    if(_zz_180_)begin
-      if(_zz_181_)begin
-        if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin
-          _zz_135_ = 1'b1;
-        end
-      end
-    end
-    if((! decode_RS2_USE))begin
-      _zz_135_ = 1'b0;
-    end
-  end
-
-  assign _zz_136_ = (_zz_49_ && writeBack_arbitration_isFiring);
-  assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2);
-  assign _zz_139_ = execute_INSTRUCTION[14 : 12];
-  always @ (*) begin
-    if((_zz_139_ == (3'b000))) begin
-        _zz_140_ = execute_BranchPlugin_eq;
-    end else if((_zz_139_ == (3'b001))) begin
-        _zz_140_ = (! execute_BranchPlugin_eq);
-    end else if((((_zz_139_ & (3'b101)) == (3'b101)))) begin
-        _zz_140_ = (! execute_SRC_LESS);
-    end else begin
-        _zz_140_ = execute_SRC_LESS;
-    end
-  end
-
-  always @ (*) begin
-    case(execute_BRANCH_CTRL)
-      `BranchCtrlEnum_defaultEncoding_INC : begin
-        _zz_141_ = 1'b0;
-      end
-      `BranchCtrlEnum_defaultEncoding_JAL : begin
-        _zz_141_ = 1'b1;
-      end
-      `BranchCtrlEnum_defaultEncoding_JALR : begin
-        _zz_141_ = 1'b1;
-      end
-      default : begin
-        _zz_141_ = _zz_140_;
-      end
-    endcase
-  end
-
-  assign _zz_33_ = _zz_141_;
-  assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC);
-  assign _zz_142_ = _zz_228_[19];
-  always @ (*) begin
-    _zz_143_[10] = _zz_142_;
-    _zz_143_[9] = _zz_142_;
-    _zz_143_[8] = _zz_142_;
-    _zz_143_[7] = _zz_142_;
-    _zz_143_[6] = _zz_142_;
-    _zz_143_[5] = _zz_142_;
-    _zz_143_[4] = _zz_142_;
-    _zz_143_[3] = _zz_142_;
-    _zz_143_[2] = _zz_142_;
-    _zz_143_[1] = _zz_142_;
-    _zz_143_[0] = _zz_142_;
-  end
-
-  assign _zz_144_ = _zz_229_[11];
-  always @ (*) begin
-    _zz_145_[19] = _zz_144_;
-    _zz_145_[18] = _zz_144_;
-    _zz_145_[17] = _zz_144_;
-    _zz_145_[16] = _zz_144_;
-    _zz_145_[15] = _zz_144_;
-    _zz_145_[14] = _zz_144_;
-    _zz_145_[13] = _zz_144_;
-    _zz_145_[12] = _zz_144_;
-    _zz_145_[11] = _zz_144_;
-    _zz_145_[10] = _zz_144_;
-    _zz_145_[9] = _zz_144_;
-    _zz_145_[8] = _zz_144_;
-    _zz_145_[7] = _zz_144_;
-    _zz_145_[6] = _zz_144_;
-    _zz_145_[5] = _zz_144_;
-    _zz_145_[4] = _zz_144_;
-    _zz_145_[3] = _zz_144_;
-    _zz_145_[2] = _zz_144_;
-    _zz_145_[1] = _zz_144_;
-    _zz_145_[0] = _zz_144_;
-  end
-
-  assign _zz_146_ = _zz_230_[11];
-  always @ (*) begin
-    _zz_147_[18] = _zz_146_;
-    _zz_147_[17] = _zz_146_;
-    _zz_147_[16] = _zz_146_;
-    _zz_147_[15] = _zz_146_;
-    _zz_147_[14] = _zz_146_;
-    _zz_147_[13] = _zz_146_;
-    _zz_147_[12] = _zz_146_;
-    _zz_147_[11] = _zz_146_;
-    _zz_147_[10] = _zz_146_;
-    _zz_147_[9] = _zz_146_;
-    _zz_147_[8] = _zz_146_;
-    _zz_147_[7] = _zz_146_;
-    _zz_147_[6] = _zz_146_;
-    _zz_147_[5] = _zz_146_;
-    _zz_147_[4] = _zz_146_;
-    _zz_147_[3] = _zz_146_;
-    _zz_147_[2] = _zz_146_;
-    _zz_147_[1] = _zz_146_;
-    _zz_147_[0] = _zz_146_;
-  end
-
-  always @ (*) begin
-    case(execute_BRANCH_CTRL)
-      `BranchCtrlEnum_defaultEncoding_JAL : begin
-        _zz_148_ = {{_zz_143_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0};
-      end
-      `BranchCtrlEnum_defaultEncoding_JALR : begin
-        _zz_148_ = {_zz_145_,execute_INSTRUCTION[31 : 20]};
-      end
-      default : begin
-        _zz_148_ = {{_zz_147_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0};
-      end
-    endcase
-  end
-
-  assign execute_BranchPlugin_branch_src2 = _zz_148_;
-  assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2);
-  assign _zz_31_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)};
-  assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0));
-  assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC;
-  assign BranchPlugin_branchExceptionPort_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]);
-  assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000);
-  assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload;
-  always @ (*) begin
-    CsrPlugin_privilege = (2'b11);
-    if(CsrPlugin_forceMachineWire)begin
-      CsrPlugin_privilege = (2'b11);
-    end
-  end
-
-  assign CsrPlugin_misa_base = (2'b01);
-  assign CsrPlugin_misa_extensions = (26'b00000000000000000001000010);
-  assign _zz_149_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE);
-  assign _zz_150_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE);
-  assign _zz_151_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE);
-  assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11);
-  assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege);
-  assign _zz_152_ = {decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid};
-  assign _zz_153_ = _zz_231_[0];
-  assign _zz_154_ = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid};
-  assign _zz_155_ = _zz_233_[0];
-  always @ (*) begin
-    CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
-    if(_zz_166_)begin
-      CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1;
-    end
-    if(decode_arbitration_isFlushed)begin
-      CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0;
-    end
-  end
-
-  always @ (*) begin
-    CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
-    if(CsrPlugin_selfException_valid)begin
-      CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1;
-    end
-    if(execute_arbitration_isFlushed)begin
-      CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0;
-    end
-  end
-
-  always @ (*) begin
-    CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
-    if(_zz_168_)begin
-      CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1;
-    end
-    if(memory_arbitration_isFlushed)begin
-      CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0;
-    end
-  end
-
-  always @ (*) begin
-    CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
-    if(writeBack_arbitration_isFlushed)begin
-      CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0;
-    end
-  end
-
-  assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
-  assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
-  assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
-  assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
-  assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException);
-  assign CsrPlugin_lastStageWasWfi = 1'b0;
-  always @ (*) begin
-    CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusSimplePlugin_pcValids_3);
-    if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin
-      CsrPlugin_pipelineLiberator_done = 1'b0;
-    end
-    if(CsrPlugin_hadException)begin
-      CsrPlugin_pipelineLiberator_done = 1'b0;
-    end
-  end
-
-  assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts);
-  always @ (*) begin
-    CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege;
-    if(CsrPlugin_hadException)begin
-      CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
-    end
-  end
-
-  always @ (*) begin
-    CsrPlugin_trapCause = CsrPlugin_interrupt_code;
-    if(CsrPlugin_hadException)begin
-      CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code;
-    end
-  end
-
-  always @ (*) begin
-    CsrPlugin_xtvec_mode = (2'bxx);
-    case(CsrPlugin_targetPrivilege)
-      2'b11 : begin
-        CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode;
-      end
-      default : begin
-      end
-    endcase
-  end
-
-  always @ (*) begin
-    CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
-    case(CsrPlugin_targetPrivilege)
-      2'b11 : begin
-        CsrPlugin_xtvec_base = CsrPlugin_mtvec_base;
-      end
-      default : begin
-      end
-    endcase
-  end
-
-  assign contextSwitching = CsrPlugin_jumpInterface_valid;
-  assign _zz_29_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000)))));
-  assign _zz_28_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000));
-  assign execute_CsrPlugin_inWfi = 1'b0;
-  assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00));
-  always @ (*) begin
-    execute_CsrPlugin_illegalAccess = 1'b1;
-    case(execute_CsrPlugin_csrAddress)
-      12'b101111000000 : begin
-        execute_CsrPlugin_illegalAccess = 1'b0;
-      end
-      12'b001100000000 : begin
-        execute_CsrPlugin_illegalAccess = 1'b0;
-      end
-      12'b001101000001 : begin
-        execute_CsrPlugin_illegalAccess = 1'b0;
-      end
-      12'b001100000101 : begin
-        if(execute_CSR_WRITE_OPCODE)begin
-          execute_CsrPlugin_illegalAccess = 1'b0;
-        end
-      end
-      12'b001101000100 : begin
-        execute_CsrPlugin_illegalAccess = 1'b0;
-      end
-      12'b001101000011 : begin
-        if(execute_CSR_READ_OPCODE)begin
-          execute_CsrPlugin_illegalAccess = 1'b0;
-        end
-      end
-      12'b111111000000 : begin
-        if(execute_CSR_READ_OPCODE)begin
-          execute_CsrPlugin_illegalAccess = 1'b0;
-        end
-      end
-      12'b001100000100 : begin
-        execute_CsrPlugin_illegalAccess = 1'b0;
-      end
-      12'b001101000010 : begin
-        if(execute_CSR_READ_OPCODE)begin
-          execute_CsrPlugin_illegalAccess = 1'b0;
-        end
-      end
-      default : begin
-      end
-    endcase
-    if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin
-      execute_CsrPlugin_illegalAccess = 1'b1;
-    end
-    if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin
-      execute_CsrPlugin_illegalAccess = 1'b0;
-    end
-  end
-
-  always @ (*) begin
-    execute_CsrPlugin_illegalInstruction = 1'b0;
-    if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin
-      if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin
-        execute_CsrPlugin_illegalInstruction = 1'b1;
-      end
-    end
-  end
-
-  always @ (*) begin
-    CsrPlugin_selfException_valid = 1'b0;
-    if(_zz_182_)begin
-      CsrPlugin_selfException_valid = 1'b1;
-    end
-  end
-
-  always @ (*) begin
-    CsrPlugin_selfException_payload_code = (4'bxxxx);
-    if(_zz_182_)begin
-      case(CsrPlugin_privilege)
-        2'b00 : begin
-          CsrPlugin_selfException_payload_code = (4'b1000);
-        end
-        default : begin
-          CsrPlugin_selfException_payload_code = (4'b1011);
-        end
-      endcase
-    end
-  end
-
-  assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION;
-  always @ (*) begin
-    execute_CsrPlugin_readData = (32'b00000000000000000000000000000000);
-    case(execute_CsrPlugin_csrAddress)
-      12'b101111000000 : begin
-        execute_CsrPlugin_readData[31 : 0] = _zz_156_;
-      end
-      12'b001100000000 : begin
-        execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP;
-        execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE;
-        execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE;
-      end
-      12'b001101000001 : begin
-        execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc;
-      end
-      12'b001100000101 : begin
-      end
-      12'b001101000100 : begin
-        execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP;
-        execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP;
-        execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP;
-      end
-      12'b001101000011 : begin
-        execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval;
-      end
-      12'b111111000000 : begin
-        execute_CsrPlugin_readData[31 : 0] = _zz_157_;
-      end
-      12'b001100000100 : begin
-        execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE;
-        execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE;
-        execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE;
-      end
-      12'b001101000010 : begin
-        execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt;
-        execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode;
-      end
-      default : begin
-      end
-    endcase
-  end
-
-  assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE);
-  assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE);
-  assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers));
-  assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers));
-  assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData;
-  always @ (*) begin
-    case(_zz_189_)
-      1'b0 : begin
-        execute_CsrPlugin_writeData = execute_SRC1;
-      end
-      default : begin
-        execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1));
-      end
-    endcase
-  end
-
-  assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20];
-  assign _zz_157_ = (_zz_156_ & externalInterruptArray_regNext);
-  assign externalInterrupt = (_zz_157_ != (32'b00000000000000000000000000000000));
-  assign _zz_25_ = decode_ALU_BITWISE_CTRL;
-  assign _zz_23_ = _zz_58_;
-  assign _zz_47_ = decode_to_execute_ALU_BITWISE_CTRL;
-  assign _zz_22_ = decode_SHIFT_CTRL;
-  assign _zz_20_ = _zz_70_;
-  assign _zz_35_ = decode_to_execute_SHIFT_CTRL;
-  assign _zz_19_ = decode_ALU_CTRL;
-  assign _zz_17_ = _zz_60_;
-  assign _zz_45_ = decode_to_execute_ALU_CTRL;
-  assign _zz_16_ = decode_BRANCH_CTRL;
-  assign _zz_14_ = _zz_59_;
-  assign _zz_32_ = decode_to_execute_BRANCH_CTRL;
-  assign _zz_13_ = decode_SRC1_CTRL;
-  assign _zz_11_ = _zz_65_;
-  assign _zz_42_ = decode_to_execute_SRC1_CTRL;
-  assign _zz_10_ = decode_ENV_CTRL;
-  assign _zz_7_ = execute_ENV_CTRL;
-  assign _zz_5_ = memory_ENV_CTRL;
-  assign _zz_8_ = _zz_55_;
-  assign _zz_27_ = decode_to_execute_ENV_CTRL;
-  assign _zz_26_ = execute_to_memory_ENV_CTRL;
-  assign _zz_30_ = memory_to_writeBack_ENV_CTRL;
-  assign _zz_3_ = decode_SRC2_CTRL;
-  assign _zz_1_ = _zz_62_;
-  assign _zz_40_ = decode_to_execute_SRC2_CTRL;
-  assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000)));
-  assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000)));
-  assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00)));
-  assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0)));
-  assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
-  assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers);
-  assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
-  assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt));
-  assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
-  assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers);
-  assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
-  assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt));
-  assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck));
-  assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers);
-  assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
-  assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt));
-  assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0);
-  assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers);
-  assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt));
-  assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt));
-  assign iBus_cmd_ready = ((1'b1 && (! iBus_cmd_m2sPipe_valid)) || iBus_cmd_m2sPipe_ready);
-  assign iBus_cmd_m2sPipe_valid = _zz_158_;
-  assign iBus_cmd_m2sPipe_payload_pc = _zz_159_;
-  assign iBusWishbone_ADR = (iBus_cmd_m2sPipe_payload_pc >>> 2);
-  assign iBusWishbone_CTI = (3'b000);
-  assign iBusWishbone_BTE = (2'b00);
-  assign iBusWishbone_SEL = (4'b1111);
-  assign iBusWishbone_WE = 1'b0;
-  assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
-  assign iBusWishbone_CYC = iBus_cmd_m2sPipe_valid;
-  assign iBusWishbone_STB = iBus_cmd_m2sPipe_valid;
-  assign iBus_cmd_m2sPipe_ready = (iBus_cmd_m2sPipe_valid && iBusWishbone_ACK);
-  assign iBus_rsp_valid = (iBusWishbone_CYC && iBusWishbone_ACK);
-  assign iBus_rsp_payload_inst = iBusWishbone_DAT_MISO;
-  assign iBus_rsp_payload_error = 1'b0;
-  assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid;
-  assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr;
-  assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address;
-  assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data;
-  assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size;
-  assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready;
-  assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2);
-  assign dBusWishbone_CTI = (3'b000);
-  assign dBusWishbone_BTE = (2'b00);
-  always @ (*) begin
-    case(dBus_cmd_halfPipe_payload_size)
-      2'b00 : begin
-        _zz_160_ = (4'b0001);
-      end
-      2'b01 : begin
-        _zz_160_ = (4'b0011);
-      end
-      default : begin
-        _zz_160_ = (4'b1111);
-      end
-    endcase
-  end
-
-  always @ (*) begin
-    dBusWishbone_SEL = _zz_241_[3:0];
-    if((! dBus_cmd_halfPipe_payload_wr))begin
-      dBusWishbone_SEL = (4'b1111);
-    end
-  end
-
-  assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr;
-  assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data;
-  assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK);
-  assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid;
-  assign dBusWishbone_STB = dBus_cmd_halfPipe_valid;
-  assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK);
-  assign dBus_rsp_data = dBusWishbone_DAT_MISO;
-  assign dBus_rsp_error = 1'b0;
-  always @ (posedge clk) begin
-    if(reset) begin
-      IBusSimplePlugin_fetchPc_pcReg <= externalResetVector;
-      IBusSimplePlugin_fetchPc_booted <= 1'b0;
-      IBusSimplePlugin_fetchPc_inc <= 1'b0;
-      _zz_99_ <= 1'b0;
-      _zz_100_ <= 1'b0;
-      IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0;
-      IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0;
-      IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0;
-      IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0;
-      IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0;
-      IBusSimplePlugin_injector_decodeRemoved <= 1'b0;
-      IBusSimplePlugin_pendingCmd <= (3'b000);
-      IBusSimplePlugin_rspJoin_discardCounter <= (3'b000);
-      _zz_125_ <= 1'b1;
-      execute_LightShifterPlugin_isActive <= 1'b0;
-      _zz_137_ <= 1'b0;
-      CsrPlugin_mstatus_MIE <= 1'b0;
-      CsrPlugin_mstatus_MPIE <= 1'b0;
-      CsrPlugin_mstatus_MPP <= (2'b11);
-      CsrPlugin_mie_MEIE <= 1'b0;
-      CsrPlugin_mie_MTIE <= 1'b0;
-      CsrPlugin_mie_MSIE <= 1'b0;
-      CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
-      CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0;
-      CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0;
-      CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
-      CsrPlugin_interrupt_valid <= 1'b0;
-      CsrPlugin_hadException <= 1'b0;
-      execute_CsrPlugin_wfiWake <= 1'b0;
-      _zz_156_ <= (32'b00000000000000000000000000000000);
-      execute_arbitration_isValid <= 1'b0;
-      memory_arbitration_isValid <= 1'b0;
-      writeBack_arbitration_isValid <= 1'b0;
-      memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000);
-      memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000);
-      _zz_158_ <= 1'b0;
-      dBus_cmd_halfPipe_regs_valid <= 1'b0;
-      dBus_cmd_halfPipe_regs_ready <= 1'b1;
-    end else begin
-      IBusSimplePlugin_fetchPc_booted <= 1'b1;
-      if((IBusSimplePlugin_fetchPc_corrected || IBusSimplePlugin_fetchPc_pcRegPropagate))begin
-        IBusSimplePlugin_fetchPc_inc <= 1'b0;
-      end
-      if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin
-        IBusSimplePlugin_fetchPc_inc <= 1'b1;
-      end
-      if(((! IBusSimplePlugin_fetchPc_output_valid) && IBusSimplePlugin_fetchPc_output_ready))begin
-        IBusSimplePlugin_fetchPc_inc <= 1'b0;
-      end
-      if((IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetcherflushIt) || IBusSimplePlugin_fetchPc_pcRegPropagate)))begin
-        IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc;
-      end
-      if(IBusSimplePlugin_fetcherflushIt)begin
-        _zz_99_ <= 1'b0;
-      end
-      if(_zz_97_)begin
-        _zz_99_ <= IBusSimplePlugin_iBusRsp_stages_0_output_valid;
-      end
-      if(IBusSimplePlugin_iBusRsp_inputBeforeStage_ready)begin
-        _zz_100_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_valid;
-      end
-      if(IBusSimplePlugin_fetcherflushIt)begin
-        _zz_100_ <= 1'b0;
-      end
-      if(IBusSimplePlugin_fetcherflushIt)begin
-        IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0;
-      end
-      if((! (! IBusSimplePlugin_iBusRsp_stages_1_input_ready)))begin
-        IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b1;
-      end
-      if(IBusSimplePlugin_fetcherflushIt)begin
-        IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0;
-      end
-      if((! (! IBusSimplePlugin_injector_decodeInput_ready)))begin
-        IBusSimplePlugin_injector_nextPcCalc_valids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_0;
-      end
-      if(IBusSimplePlugin_fetcherflushIt)begin
-        IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0;
-      end
-      if(IBusSimplePlugin_fetcherflushIt)begin
-        IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0;
-      end
-      if((! execute_arbitration_isStuck))begin
-        IBusSimplePlugin_injector_nextPcCalc_valids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_1;
-      end
-      if(IBusSimplePlugin_fetcherflushIt)begin
-        IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0;
-      end
-      if(IBusSimplePlugin_fetcherflushIt)begin
-        IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0;
-      end
-      if((! memory_arbitration_isStuck))begin
-        IBusSimplePlugin_injector_nextPcCalc_valids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_2;
-      end
-      if(IBusSimplePlugin_fetcherflushIt)begin
-        IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0;
-      end
-      if(IBusSimplePlugin_fetcherflushIt)begin
-        IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0;
-      end
-      if((! writeBack_arbitration_isStuck))begin
-        IBusSimplePlugin_injector_nextPcCalc_valids_4 <= IBusSimplePlugin_injector_nextPcCalc_valids_3;
-      end
-      if(IBusSimplePlugin_fetcherflushIt)begin
-        IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0;
-      end
-      if(decode_arbitration_removeIt)begin
-        IBusSimplePlugin_injector_decodeRemoved <= 1'b1;
-      end
-      if(IBusSimplePlugin_fetcherflushIt)begin
-        IBusSimplePlugin_injector_decodeRemoved <= 1'b0;
-      end
-      IBusSimplePlugin_pendingCmd <= IBusSimplePlugin_pendingCmdNext;
-      IBusSimplePlugin_rspJoin_discardCounter <= (IBusSimplePlugin_rspJoin_discardCounter - _zz_199_);
-      if(IBusSimplePlugin_fetcherflushIt)begin
-        IBusSimplePlugin_rspJoin_discardCounter <= (IBusSimplePlugin_pendingCmd - _zz_201_);
-      end
-      _zz_125_ <= 1'b0;
-      if(_zz_164_)begin
-        if(_zz_167_)begin
-          execute_LightShifterPlugin_isActive <= 1'b1;
-          if(execute_LightShifterPlugin_done)begin
-            execute_LightShifterPlugin_isActive <= 1'b0;
-          end
-        end
-      end
-      if(execute_arbitration_removeIt)begin
-        execute_LightShifterPlugin_isActive <= 1'b0;
-      end
-      _zz_137_ <= _zz_136_;
-      if((! decode_arbitration_isStuck))begin
-        CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
-      end else begin
-        CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
-      end
-      if((! execute_arbitration_isStuck))begin
-        CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck));
-      end else begin
-        CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
-      end
-      if((! memory_arbitration_isStuck))begin
-        CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck));
-      end else begin
-        CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
-      end
-      if((! writeBack_arbitration_isStuck))begin
-        CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck));
-      end else begin
-        CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
-      end
-      CsrPlugin_interrupt_valid <= 1'b0;
-      if(_zz_183_)begin
-        if(_zz_184_)begin
-          CsrPlugin_interrupt_valid <= 1'b1;
-        end
-        if(_zz_185_)begin
-          CsrPlugin_interrupt_valid <= 1'b1;
-        end
-        if(_zz_186_)begin
-          CsrPlugin_interrupt_valid <= 1'b1;
-        end
-      end
-      CsrPlugin_hadException <= CsrPlugin_exception;
-      if(_zz_169_)begin
-        case(CsrPlugin_targetPrivilege)
-          2'b11 : begin
-            CsrPlugin_mstatus_MIE <= 1'b0;
-            CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE;
-            CsrPlugin_mstatus_MPP <= CsrPlugin_privilege;
-          end
-          default : begin
-          end
-        endcase
-      end
-      if(_zz_170_)begin
-        case(_zz_171_)
-          2'b11 : begin
-            CsrPlugin_mstatus_MPP <= (2'b00);
-            CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE;
-            CsrPlugin_mstatus_MPIE <= 1'b1;
-          end
-          default : begin
-          end
-        endcase
-      end
-      execute_CsrPlugin_wfiWake <= ({_zz_151_,{_zz_150_,_zz_149_}} != (3'b000));
-      if((! writeBack_arbitration_isStuck))begin
-        memory_to_writeBack_REGFILE_WRITE_DATA <= memory_REGFILE_WRITE_DATA;
-      end
-      if((! writeBack_arbitration_isStuck))begin
-        memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION;
-      end
-      if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin
-        execute_arbitration_isValid <= 1'b0;
-      end
-      if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin
-        execute_arbitration_isValid <= decode_arbitration_isValid;
-      end
-      if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin
-        memory_arbitration_isValid <= 1'b0;
-      end
-      if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin
-        memory_arbitration_isValid <= execute_arbitration_isValid;
-      end
-      if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin
-        writeBack_arbitration_isValid <= 1'b0;
-      end
-      if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin
-        writeBack_arbitration_isValid <= memory_arbitration_isValid;
-      end
-      case(execute_CsrPlugin_csrAddress)
-        12'b101111000000 : begin
-          if(execute_CsrPlugin_writeEnable)begin
-            _zz_156_ <= execute_CsrPlugin_writeData[31 : 0];
-          end
-        end
-        12'b001100000000 : begin
-          if(execute_CsrPlugin_writeEnable)begin
-            CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11];
-            CsrPlugin_mstatus_MPIE <= _zz_235_[0];
-            CsrPlugin_mstatus_MIE <= _zz_236_[0];
-          end
-        end
-        12'b001101000001 : begin
-        end
-        12'b001100000101 : begin
-        end
-        12'b001101000100 : begin
-        end
-        12'b001101000011 : begin
-        end
-        12'b111111000000 : begin
-        end
-        12'b001100000100 : begin
-          if(execute_CsrPlugin_writeEnable)begin
-            CsrPlugin_mie_MEIE <= _zz_238_[0];
-            CsrPlugin_mie_MTIE <= _zz_239_[0];
-            CsrPlugin_mie_MSIE <= _zz_240_[0];
-          end
-        end
-        12'b001101000010 : begin
-        end
-        default : begin
-        end
-      endcase
-      if(iBus_cmd_ready)begin
-        _zz_158_ <= iBus_cmd_valid;
-      end
-      if(_zz_187_)begin
-        dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid;
-        dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid);
-      end else begin
-        dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready);
-        dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready;
-      end
-    end
-  end
-
-  always @ (posedge clk) begin
-    if(IBusSimplePlugin_iBusRsp_inputBeforeStage_ready)begin
-      _zz_101_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc;
-      _zz_102_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error;
-      _zz_103_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst;
-      _zz_104_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc;
-    end
-    if(IBusSimplePlugin_injector_decodeInput_ready)begin
-      IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst;
-    end
-    if(IBusSimplePlugin_iBusRsp_stages_1_output_ready)begin
-      IBusSimplePlugin_mmu_joinCtx_physicalAddress <= IBusSimplePlugin_mmuBus_rsp_physicalAddress;
-      IBusSimplePlugin_mmu_joinCtx_isIoAccess <= IBusSimplePlugin_mmuBus_rsp_isIoAccess;
-      IBusSimplePlugin_mmu_joinCtx_allowRead <= IBusSimplePlugin_mmuBus_rsp_allowRead;
-      IBusSimplePlugin_mmu_joinCtx_allowWrite <= IBusSimplePlugin_mmuBus_rsp_allowWrite;
-      IBusSimplePlugin_mmu_joinCtx_allowExecute <= IBusSimplePlugin_mmuBus_rsp_allowExecute;
-      IBusSimplePlugin_mmu_joinCtx_exception <= IBusSimplePlugin_mmuBus_rsp_exception;
-      IBusSimplePlugin_mmu_joinCtx_refilling <= IBusSimplePlugin_mmuBus_rsp_refilling;
-    end
-    if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin
-      $display("ERROR DBusSimplePlugin doesn't allow memory stage stall when read happend");
-    end
-    if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin
-      $display("ERROR DBusSimplePlugin doesn't allow writeback stage stall when read happend");
-    end
-    if(_zz_164_)begin
-      if(_zz_167_)begin
-        execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001));
-      end
-    end
-    if(_zz_136_)begin
-      _zz_138_ <= _zz_48_[11 : 7];
-    end
-    CsrPlugin_mip_MEIP <= externalInterrupt;
-    CsrPlugin_mip_MTIP <= timerInterrupt;
-    CsrPlugin_mip_MSIP <= softwareInterrupt;
-    CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001));
-    if(writeBack_arbitration_isFiring)begin
-      CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001));
-    end
-    if(_zz_166_)begin
-      CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_153_ ? IBusSimplePlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code);
-      CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_153_ ? IBusSimplePlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr);
-    end
-    if(CsrPlugin_selfException_valid)begin
-      CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code;
-      CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr;
-    end
-    if(_zz_168_)begin
-      CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_155_ ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code);
-      CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_155_ ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr);
-    end
-    if(_zz_183_)begin
-      if(_zz_184_)begin
-        CsrPlugin_interrupt_code <= (4'b0111);
-        CsrPlugin_interrupt_targetPrivilege <= (2'b11);
-      end
-      if(_zz_185_)begin
-        CsrPlugin_interrupt_code <= (4'b0011);
-        CsrPlugin_interrupt_targetPrivilege <= (2'b11);
-      end
-      if(_zz_186_)begin
-        CsrPlugin_interrupt_code <= (4'b1011);
-        CsrPlugin_interrupt_targetPrivilege <= (2'b11);
-      end
-    end
-    if(_zz_169_)begin
-      case(CsrPlugin_targetPrivilege)
-        2'b11 : begin
-          CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException);
-          CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause;
-          CsrPlugin_mepc <= writeBack_PC;
-          if(CsrPlugin_hadException)begin
-            CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
-          end
-        end
-        default : begin
-        end
-      endcase
-    end
-    externalInterruptArray_regNext <= externalInterruptArray;
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_ALU_BITWISE_CTRL <= _zz_24_;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_SHIFT_CTRL <= _zz_21_;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_MMU_FAULT <= execute_MMU_FAULT;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_MMU_RSP_physicalAddress <= execute_MMU_RSP_physicalAddress;
-      execute_to_memory_MMU_RSP_isIoAccess <= execute_MMU_RSP_isIoAccess;
-      execute_to_memory_MMU_RSP_allowRead <= execute_MMU_RSP_allowRead;
-      execute_to_memory_MMU_RSP_allowWrite <= execute_MMU_RSP_allowWrite;
-      execute_to_memory_MMU_RSP_allowExecute <= execute_MMU_RSP_allowExecute;
-      execute_to_memory_MMU_RSP_exception <= execute_MMU_RSP_exception;
-      execute_to_memory_MMU_RSP_refilling <= execute_MMU_RSP_refilling;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_ALU_CTRL <= _zz_18_;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_BRANCH_CTRL <= _zz_15_;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_SRC1_CTRL <= _zz_12_;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW;
-    end
-    if((! writeBack_arbitration_isStuck))begin
-      memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_ENV_CTRL <= _zz_9_;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_ENV_CTRL <= _zz_6_;
-    end
-    if((! writeBack_arbitration_isStuck))begin
-      memory_to_writeBack_ENV_CTRL <= _zz_4_;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_RS2 <= decode_RS2;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_IS_CSR <= decode_IS_CSR;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE;
-    end
-    if((! writeBack_arbitration_isStuck))begin
-      memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE;
-    end
-    if((! writeBack_arbitration_isStuck))begin
-      memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_FORMAL_PC_NEXT <= _zz_85_;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT;
-    end
-    if((! writeBack_arbitration_isStuck))begin
-      memory_to_writeBack_FORMAL_PC_NEXT <= _zz_84_;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE;
-    end
-    if((! writeBack_arbitration_isStuck))begin
-      memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_PC <= decode_PC;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_PC <= _zz_39_;
-    end
-    if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin
-      memory_to_writeBack_PC <= memory_PC;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE;
-    end
-    if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin
-      execute_to_memory_REGFILE_WRITE_DATA <= _zz_34_;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_SRC2_CTRL <= _zz_2_;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_INSTRUCTION <= decode_INSTRUCTION;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_INSTRUCTION <= execute_INSTRUCTION;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_BRANCH_DO <= execute_BRANCH_DO;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_RS1 <= decode_RS1;
-    end
-    if((! execute_arbitration_isStuck))begin
-      decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID;
-    end
-    if((! memory_arbitration_isStuck))begin
-      execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID;
-    end
-    if((! writeBack_arbitration_isStuck))begin
-      memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID;
-    end
-    case(execute_CsrPlugin_csrAddress)
-      12'b101111000000 : begin
-      end
-      12'b001100000000 : begin
-      end
-      12'b001101000001 : begin
-        if(execute_CsrPlugin_writeEnable)begin
-          CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0];
-        end
-      end
-      12'b001100000101 : begin
-        if(execute_CsrPlugin_writeEnable)begin
-          CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2];
-          CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0];
-        end
-      end
-      12'b001101000100 : begin
-        if(execute_CsrPlugin_writeEnable)begin
-          CsrPlugin_mip_MSIP <= _zz_237_[0];
-        end
-      end
-      12'b001101000011 : begin
-      end
-      12'b111111000000 : begin
-      end
-      12'b001100000100 : begin
-      end
-      12'b001101000010 : begin
-      end
-      default : begin
-      end
-    endcase
-    if(iBus_cmd_ready)begin
-      _zz_159_ <= iBus_cmd_payload_pc;
-    end
-    if(_zz_187_)begin
-      dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr;
-      dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address;
-      dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data;
-      dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size;
-    end
-  end
-
-endmodule
-
diff --git a/litedram/extras/fusesoc-add-files.py b/litedram/extras/fusesoc-add-files.py
index 32681d6..aad9476 100644
--- a/litedram/extras/fusesoc-add-files.py
+++ b/litedram/extras/fusesoc-add-files.py
@@ -17,15 +17,6 @@ class LiteDRAMGenerator(Generator):
 
         print("Adding LiteDRAM for board... ", board)
 
-        # Grab init-cpu.txt if it exists
-        cpu_file = os.path.join(gen_dir, "init-cpu.txt")
-        if os.path.exists(cpu_file):
-            cpu = pathlib.Path(cpu_file).read_text()
-        else:
-            cpu = "none"
-
-        print("CPU is ", cpu)
-
         # Add files to fusesoc
         files = []
         f = os.path.join(gen_dir, "litedram_core.v")
@@ -34,18 +25,8 @@ class LiteDRAMGenerator(Generator):
         files.append({f : {'file_type' : 'vhdlSource-2008'}})
         f = os.path.join(gen_dir, "litedram_core.init")
         files.append({f : {'file_type' : 'user'}})
-
-        # Look for init CPU types and add corresponding files
-        if cpu == "vexriscv":
-            print("Adding VexRiscv files and wrapper")
-            f = os.path.join(extras_dir, "VexRiscv.v")
-            files.append({f : {'file_type' : 'verilogSource'}})
-            f = os.path.join(extras_dir, "wrapper-self-init.vhdl")
-            files.append({f : {'file_type' : 'vhdlSource-2008'}})
-        else:
-            print("Adding wrapper")
-            f = os.path.join(extras_dir, "wrapper-mw-init.vhdl")
-            files.append({f : {'file_type' : 'vhdlSource-2008'}})
+        f = os.path.join(extras_dir, "litedram-wrapper-l2.vhdl")
+        files.append({f : {'file_type' : 'vhdlSource-2008'}})
 
         self.add_files(files)
 
diff --git a/litedram/extras/litedram-wrapper-l2.vhdl b/litedram/extras/litedram-wrapper-l2.vhdl
new file mode 100644
index 0000000..6bd3636
--- /dev/null
+++ b/litedram/extras/litedram-wrapper-l2.vhdl
@@ -0,0 +1,1039 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.wishbone_types.all;
+use work.utils.all;
+use work.helpers.all;
+
+entity litedram_wrapper is
+    generic (
+	DRAM_ABITS     : positive;
+	DRAM_ALINES    : positive;
+
+        -- Pseudo-ROM payload
+        PAYLOAD_SIZE      : natural;    
+        PAYLOAD_FILE      : string;
+
+        -- L2 cache --
+
+        -- Line size in bytes
+        LINE_SIZE         : positive := 128;
+        -- Number of lines in a set
+        NUM_LINES         : positive := 32;
+        -- Number of ways
+        NUM_WAYS          : positive := 4;
+        -- Max number of stores in the queue
+        STOREQ_DEPTH      : positive := 8;
+        -- Don't send loads until all pending stores acked in litedram
+        NO_LS_OVERLAP     : boolean  := false;
+
+        -- Debug
+        LITEDRAM_TRACE    : boolean  := false;
+        TRACE             : boolean  := false
+        );
+    port(
+        -- LiteDRAM generates the system clock and reset
+        -- from the input clkin
+        clk_in          : in std_ulogic;
+        rst             : in std_ulogic;
+        system_clk      : out std_ulogic;
+        system_reset    : out std_ulogic;
+        core_alt_reset  : out std_ulogic;
+        pll_locked      : out std_ulogic;
+
+        -- Wishbone ports:
+        wb_in           : in wishbone_master_out;
+        wb_out          : out wishbone_slave_out;
+        wb_ctrl_in      : in wb_io_master_out;
+        wb_ctrl_out     : out wb_io_slave_out;
+        wb_ctrl_is_csr  : in std_ulogic;
+        wb_ctrl_is_init : in std_ulogic;
+
+        -- Init core serial debug
+        serial_tx     : out std_ulogic;
+        serial_rx     : in std_ulogic;
+
+        -- Misc
+        init_done     : out std_ulogic;
+        init_error    : out std_ulogic;
+
+        -- DRAM wires
+        ddram_a       : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
+        ddram_ba      : out std_ulogic_vector(2 downto 0);
+        ddram_ras_n   : out std_ulogic;
+        ddram_cas_n   : out std_ulogic;
+        ddram_we_n    : out std_ulogic;
+        ddram_cs_n    : out std_ulogic;
+        ddram_dm      : out std_ulogic_vector(1 downto 0);
+        ddram_dq      : inout std_ulogic_vector(15 downto 0);
+        ddram_dqs_p   : inout std_ulogic_vector(1 downto 0);
+        ddram_dqs_n   : inout std_ulogic_vector(1 downto 0);
+        ddram_clk_p   : out std_ulogic;
+        ddram_clk_n   : out std_ulogic;
+        ddram_cke     : out std_ulogic;
+        ddram_odt     : out std_ulogic;
+        ddram_reset_n : out std_ulogic
+        );
+end entity litedram_wrapper;
+
+architecture behaviour of litedram_wrapper is
+
+    component litedram_core port (
+        clk                            : in std_ulogic;
+        rst                            : in std_ulogic;
+        pll_locked                     : out std_ulogic;
+        ddram_a                        : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
+        ddram_ba                       : out std_ulogic_vector(2 downto 0);
+        ddram_ras_n                    : out std_ulogic;
+        ddram_cas_n                    : out std_ulogic;
+        ddram_we_n                     : out std_ulogic;
+        ddram_cs_n                     : out std_ulogic;
+        ddram_dm                       : out std_ulogic_vector(1 downto 0);
+        ddram_dq                       : inout std_ulogic_vector(15 downto 0);
+        ddram_dqs_p                    : inout std_ulogic_vector(1 downto 0);
+        ddram_dqs_n                    : inout std_ulogic_vector(1 downto 0);
+        ddram_clk_p                    : out std_ulogic;
+        ddram_clk_n                    : out std_ulogic;
+        ddram_cke                      : out std_ulogic;
+        ddram_odt                      : out std_ulogic;
+        ddram_reset_n                  : out std_ulogic;
+        init_done                      : out std_ulogic;
+        init_error                     : out std_ulogic;
+        user_clk                       : out std_ulogic;
+        user_rst                       : out std_ulogic;
+        wb_ctrl_adr                    : in std_ulogic_vector(29 downto 0);
+        wb_ctrl_dat_w                  : in std_ulogic_vector(31 downto 0);
+        wb_ctrl_dat_r                  : out std_ulogic_vector(31 downto 0);
+        wb_ctrl_sel                    : in std_ulogic_vector(3 downto 0);
+        wb_ctrl_cyc                    : in std_ulogic;
+        wb_ctrl_stb                    : in std_ulogic;
+        wb_ctrl_ack                    : out std_ulogic;
+        wb_ctrl_we                     : in std_ulogic;
+        wb_ctrl_cti                    : in std_ulogic_vector(2 downto 0);
+        wb_ctrl_bte                    : in std_ulogic_vector(1 downto 0);
+        wb_ctrl_err                    : out std_ulogic;
+        user_port_native_0_cmd_valid   : in std_ulogic;
+        user_port_native_0_cmd_ready   : out std_ulogic;
+        user_port_native_0_cmd_we      : in std_ulogic;
+        user_port_native_0_cmd_addr    : in std_ulogic_vector(DRAM_ABITS-1 downto 0);
+        user_port_native_0_wdata_valid : in std_ulogic;
+        user_port_native_0_wdata_ready : out std_ulogic;
+        user_port_native_0_wdata_we    : in std_ulogic_vector(15 downto 0);
+        user_port_native_0_wdata_data  : in std_ulogic_vector(127 downto 0);
+        user_port_native_0_rdata_valid : out std_ulogic;
+        user_port_native_0_rdata_ready : in std_ulogic;
+        user_port_native_0_rdata_data  : out std_ulogic_vector(127 downto 0)
+        );
+    end component;
+    
+    signal user_port0_cmd_valid         : std_ulogic;
+    signal user_port0_cmd_ready         : std_ulogic;
+    signal user_port0_cmd_we            : std_ulogic;
+    signal user_port0_cmd_addr          : std_ulogic_vector(DRAM_ABITS-1 downto 0);
+    signal user_port0_wdata_valid       : std_ulogic;
+    signal user_port0_wdata_ready       : std_ulogic;
+    signal user_port0_wdata_we          : std_ulogic_vector(15 downto 0);
+    signal user_port0_wdata_data        : std_ulogic_vector(127 downto 0);
+    signal user_port0_rdata_valid       : std_ulogic;
+    signal user_port0_rdata_ready       : std_ulogic;
+    signal user_port0_rdata_data        : std_ulogic_vector(127 downto 0);
+
+    signal wb_ctrl_adr                  : std_ulogic_vector(29 downto 0);
+    signal wb_ctrl_dat_w                : std_ulogic_vector(31 downto 0);
+    signal wb_ctrl_dat_r                : std_ulogic_vector(31 downto 0);
+    signal wb_ctrl_sel                  : std_ulogic_vector(3 downto 0);
+    signal wb_ctrl_cyc                  : std_ulogic := '0';
+    signal wb_ctrl_stb                  : std_ulogic;
+    signal wb_ctrl_ack                  : std_ulogic;
+    signal wb_ctrl_we                   : std_ulogic;
+
+    signal wb_init_in                   : wb_io_master_out;
+    signal wb_init_out                  : wb_io_slave_out;
+
+    -- DRAM data port width
+    constant DRAM_DBITS                 : natural := 128;
+    constant DRAM_SBITS                 : natural := (DRAM_DBITS / 8);
+
+    -- BRAM organisation: We never access more than wishbone_data_bits at
+    -- a time so to save resources we make the array only that wide, and
+    -- use consecutive indices for to make a cache "line"
+    --
+    -- ROW_SIZE is the width in bytes of the BRAM (based on litedram, so 128-bits)
+    constant ROW_SIZE      : natural := DRAM_DBITS / 8;
+    -- ROW_PER_LINE is the number of row (litedram transactions) in a line
+    constant ROW_PER_LINE  : natural := LINE_SIZE / ROW_SIZE;
+    -- BRAM_ROWS is the number of rows in BRAM needed to represent the full
+    -- dcache
+    constant BRAM_ROWS     : natural := NUM_LINES * ROW_PER_LINE;
+
+    -- Bit fields counts in the address
+
+    -- ROW_BITS is the number of bits to select a row
+    constant ROW_BITS      : natural := log2(BRAM_ROWS);
+    -- ROW_LINEBITS is the number of bits to select a row within a line
+    constant ROW_LINEBITS  : natural := log2(ROW_PER_LINE);
+    -- LINE_OFF_BITS is the number of bits for the offset in a cache line
+    constant LINE_OFF_BITS : natural := log2(LINE_SIZE);
+    -- ROW_OFF_BITS is the number of bits for the offset in a row
+    constant ROW_OFF_BITS  : natural := log2(ROW_SIZE);
+    -- REAL_ADDR_BITS is the number of real address bits that we store
+    constant REAL_ADDR_BITS : positive := DRAM_ABITS + ROW_OFF_BITS;
+    -- INDEX_BITS is the number if bits to select a cache line
+    constant INDEX_BITS    : natural := log2(NUM_LINES);
+    -- SET_SIZE_BITS is the log base 2 of the set size
+    constant SET_SIZE_BITS : natural := LINE_OFF_BITS + INDEX_BITS;
+    -- TAG_BITS is the number of bits of the tag part of the address
+    constant TAG_BITS      : natural := REAL_ADDR_BITS - SET_SIZE_BITS;
+    -- WAY_BITS is the number of bits to select a way
+    constant WAY_BITS     : natural := log2(NUM_WAYS);
+
+    subtype row_t is integer range 0 to BRAM_ROWS-1;
+    subtype index_t is integer range 0 to NUM_LINES-1;
+    subtype way_t is integer range 0 to NUM_WAYS-1;
+
+    -- The cache data BRAM organized as described above for each way
+    subtype cache_row_t is std_ulogic_vector(DRAM_DBITS-1 downto 0);
+
+    -- The cache tags LUTRAM has a row per set. Vivado is a pain and will
+    -- not handle a clean (commented) definition of the cache tags as a 3d
+    -- memory. For now, work around it by putting all the tags
+    subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0);
+--    type cache_tags_set_t is array(way_t) of cache_tag_t;
+--    type cache_tags_array_t is array(index_t) of cache_tags_set_t;
+    constant TAG_RAM_WIDTH : natural := TAG_BITS * NUM_WAYS;
+    subtype cache_tags_set_t is std_logic_vector(TAG_RAM_WIDTH-1 downto 0);
+    type cache_tags_array_t is array(index_t) of cache_tags_set_t;
+
+    -- The cache valid bits
+    subtype cache_way_valids_t is std_ulogic_vector(NUM_WAYS-1 downto 0);
+    type cache_valids_t is array(index_t) of cache_way_valids_t;
+
+    -- Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
+    signal cache_tags   : cache_tags_array_t;
+    signal cache_valids : cache_valids_t;
+
+    attribute ram_style : string;
+    attribute ram_style of cache_tags : signal is "distributed";
+
+    --
+    -- Store queue signals
+    --
+    -- We store a single wishbone dword per entry (64-bit) but all
+    -- 16 sel bits for the DRAM.
+    -- XXX Investigate storing only AD3 and 8 sel bits if it's better
+    constant STOREQ_BITS  : positive := wishbone_data_bits + DRAM_SBITS;
+
+    signal storeq_rd_ready : std_ulogic;
+    signal storeq_rd_valid : std_ulogic;
+    signal storeq_rd_data  : std_ulogic_vector(STOREQ_BITS-1 downto 0);
+    signal storeq_wr_ready : std_ulogic;
+    signal storeq_wr_valid : std_ulogic;
+    signal storeq_wr_data  : std_ulogic_vector(STOREQ_BITS-1 downto 0);
+
+    --
+    -- Cache management signals
+    --
+
+     -- Cache state machine
+    type state_t is (IDLE,             -- Normal load hit processing
+                     REFILL_WAIT_ACK); -- Cache refill wait ack
+    signal state : state_t;
+
+    -- Latched WB request.
+    signal wb_req : wishbone_master_out := wishbone_master_out_init;
+
+    -- Read pipeline (to handle cache RAM latency)
+    signal read_ack_0  : std_ulogic;
+    signal read_ack_1  : std_ulogic;
+    signal read_ad3_0  : std_ulogic;
+    signal read_ad3_1  : std_ulogic;
+    signal read_way_0  : way_t;
+    signal read_way_1  : way_t;
+
+    -- Async signals decoding latched request
+    type req_op_t is (OP_NONE,
+                      OP_LOAD_HIT,
+                      OP_LOAD_MISS,
+                      OP_STORE_HIT,
+                      OP_STORE_MISS);
+
+    signal req_index    : index_t;
+    signal req_row      : row_t;
+    signal req_hit_way  : way_t;
+    signal req_tag      : cache_tag_t;
+    signal req_op       : req_op_t;
+    signal req_laddr    : std_ulogic_vector(REAL_ADDR_BITS-1 downto 0);
+    signal req_ad3      : std_ulogic;
+    signal req_we       : std_ulogic_vector(DRAM_SBITS-1 downto 0);
+    signal req_wdata    : std_ulogic_vector(DRAM_DBITS-1 downto 0);
+    signal accept_store : std_ulogic;
+
+    -- Line refill command signals and latches
+    signal refill_cmd_valid : std_ulogic;
+    signal refill_cmd_addr  : std_ulogic_vector(DRAM_ABITS-1 downto 0);
+    signal refill_way       : way_t;
+    signal refill_index     : index_t;
+    signal refill_row       : row_t;
+
+    -- Cache RAM interface
+    type cache_ram_out_t is array(way_t) of cache_row_t;
+    signal cache_out   : cache_ram_out_t;
+
+    -- PLRU output interface
+    type plru_out_t is array(index_t) of std_ulogic_vector(WAY_BITS-1 downto 0);
+    signal plru_victim : plru_out_t;
+
+    --
+    -- Helper functions to decode incoming requests
+    --
+
+    -- Return the cache line index (tag index) for an address
+    function get_index(addr: wishbone_addr_type) return index_t is
+    begin
+        return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto LINE_OFF_BITS)));
+    end;
+
+    -- Return the cache row index (data memory) for an address
+    function get_row(addr: std_ulogic_vector(REAL_ADDR_BITS-1 downto 0)) return row_t is
+    begin
+        return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto ROW_OFF_BITS)));
+    end;
+
+    -- Returns whether this is the last row of a line. It takes a DRAM address
+    function is_last_row_addr(addr: std_ulogic_vector(REAL_ADDR_BITS-1 downto ROW_OFF_BITS))
+        return boolean is
+        constant ones : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1');
+    begin
+        return addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS) = ones;
+    end;
+
+    -- Returns whether this is the last row of a line
+    function is_last_row(row: row_t) return boolean is
+        variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0);
+        constant ones  : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1');
+    begin
+        row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
+        return row_v(ROW_LINEBITS-1 downto 0) = ones;
+    end;
+
+    -- Return the address of the next row in the current cache line. It takes a
+    -- DRAM address
+    function next_row_addr(addr: std_ulogic_vector(REAL_ADDR_BITS-1 downto ROW_OFF_BITS))
+        return std_ulogic_vector is
+        variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
+        variable result  : std_ulogic_vector(REAL_ADDR_BITS-1 downto ROW_OFF_BITS);
+    begin
+        -- Is there no simpler way in VHDL to generate that 3 bits adder ?
+        row_idx := addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS);
+        row_idx := std_ulogic_vector(unsigned(row_idx) + 1);
+        result := addr;
+        result(LINE_OFF_BITS-1 downto ROW_OFF_BITS) := row_idx;
+        return result;
+    end;
+
+    -- Return the next row in the current cache line. We use a dedicated
+    -- function in order to limit the size of the generated adder to be
+    -- only the bits within a cache line (3 bits with default settings)
+    --
+    function next_row(row: row_t) return row_t is
+       variable row_v  : std_ulogic_vector(ROW_BITS-1 downto 0);
+       variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
+       variable result : std_ulogic_vector(ROW_BITS-1 downto 0);
+    begin
+       row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
+       row_idx := row_v(ROW_LINEBITS-1 downto 0);
+       row_v(ROW_LINEBITS-1 downto 0) := std_ulogic_vector(unsigned(row_idx) + 1);
+       return to_integer(unsigned(row_v));
+    end;
+
+    -- Get the tag value from the address
+    function get_tag(addr: wishbone_addr_type) return cache_tag_t is
+    begin
+        return addr(REAL_ADDR_BITS - 1 downto SET_SIZE_BITS);
+    end;
+
+    -- Read a tag from a tag memory row
+    function read_tag(way: way_t; tagset: cache_tags_set_t) return cache_tag_t is
+    begin
+        return tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS);
+    end;
+
+    -- Write a tag to tag memory row
+    procedure write_tag(way: in way_t; tagset: inout cache_tags_set_t;
+                        tag: cache_tag_t) is
+    begin
+        tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS) := tag;
+    end;
+
+begin
+
+    -- Sanity checks
+    assert LINE_SIZE mod ROW_SIZE = 0 report "LINE_SIZE not multiple of ROW_SIZE" severity FAILURE;
+    assert ispow2(LINE_SIZE)    report "LINE_SIZE not power of 2" severity FAILURE;
+    assert ispow2(NUM_LINES)    report "NUM_LINES not power of 2" severity FAILURE;
+    assert ispow2(ROW_PER_LINE) report "ROW_PER_LINE not power of 2" severity FAILURE;
+    assert (ROW_BITS = INDEX_BITS + ROW_LINEBITS)
+        report "geometry bits don't add up" severity FAILURE;
+    assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS)
+        report "geometry bits don't add up" severity FAILURE;
+    assert (REAL_ADDR_BITS = TAG_BITS + INDEX_BITS + LINE_OFF_BITS)
+        report "geometry bits don't add up" severity FAILURE;
+    assert (REAL_ADDR_BITS = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
+        report "geometry bits don't add up" severity FAILURE;
+    assert (128 = DRAM_DBITS)
+        report "Can't yet handle a DRAM width that isn't 128-bits" severity FAILURE;
+
+    -- alternate core reset address set when DRAM is not initialized.
+    core_alt_reset <= not init_done;
+
+    -- Init code BRAM memory slave 
+    init_ram_0: entity work.dram_init_mem
+        generic map(
+            EXTRA_PAYLOAD_FILE => PAYLOAD_FILE,
+            EXTRA_PAYLOAD_SIZE => PAYLOAD_SIZE
+            )
+        port map(
+            clk => system_clk,
+            wb_in => wb_init_in,
+            wb_out => wb_init_out
+            );
+
+    --
+    -- Control bus wishbone: This muxes the wishbone to the CSRs
+    -- and an internal small one to the init BRAM
+    --
+
+    -- Init DRAM wishbone IN signals
+    wb_init_in.adr <= wb_ctrl_in.adr;
+    wb_init_in.dat <= wb_ctrl_in.dat;
+    wb_init_in.sel <= wb_ctrl_in.sel;
+    wb_init_in.we  <= wb_ctrl_in.we;
+    wb_init_in.stb <= wb_ctrl_in.stb;
+    wb_init_in.cyc <= wb_ctrl_in.cyc and wb_ctrl_is_init;
+
+    -- DRAM CSR IN signals. Extra latch to help with timing
+    csr_latch: process(system_clk)
+    begin
+        if rising_edge(system_clk) then
+            if system_reset = '1' then
+                wb_ctrl_cyc <= '0';
+                wb_ctrl_stb <= '0';
+            else
+                -- XXX Maybe only update addr when cyc = '1' to save power ?
+                wb_ctrl_adr   <= x"0000" & wb_ctrl_in.adr(15 downto 2);
+                wb_ctrl_dat_w <= wb_ctrl_in.dat;
+                wb_ctrl_sel   <= wb_ctrl_in.sel;
+                wb_ctrl_we    <= wb_ctrl_in.we;
+                wb_ctrl_cyc   <= wb_ctrl_in.cyc and wb_ctrl_is_csr;
+                wb_ctrl_stb   <= wb_ctrl_in.stb and wb_ctrl_is_csr;
+
+                -- Clear stb on ack otherwise the memory will latch
+                -- the write twice which breaks levelling. On the next
+                -- cycle we will latch an updated stb that takes the
+                -- ack into account.
+                if wb_ctrl_ack = '1' then
+                    wb_ctrl_stb <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- Ctrl bus wishbone OUT signals. XXX Consider adding latch on
+    -- CSR response to help timing
+    wb_ctrl_out.ack   <= wb_ctrl_ack when wb_ctrl_is_csr = '1'
+                         else wb_init_out.ack;
+    wb_ctrl_out.dat   <= wb_ctrl_dat_r when wb_ctrl_is_csr = '1'
+                         else wb_init_out.dat;
+    wb_ctrl_out.stall <= wb_init_out.stall when wb_ctrl_is_init else
+                         '0' when wb_ctrl_in.cyc = '0' else not wb_ctrl_ack;
+
+
+    -- Generate a cache RAM for each way
+    rams: for i in 0 to NUM_WAYS-1 generate
+        signal do_read  : std_ulogic;
+        signal do_write : std_ulogic;
+        signal rd_addr  : std_ulogic_vector(ROW_BITS-1 downto 0);
+        signal wr_addr  : std_ulogic_vector(ROW_BITS-1 downto 0);
+        signal wr_data  : std_ulogic_vector(DRAM_DBITS-1 downto 0);
+        signal wr_sel   : std_ulogic_vector(ROW_SIZE-1 downto 0);
+        signal wr_sel_m : std_ulogic_vector(ROW_SIZE-1 downto 0);
+        signal dout     : cache_row_t;
+   begin
+        way: entity work.cache_ram
+            generic map (
+                ROW_BITS => ROW_BITS,
+                WIDTH    => DRAM_DBITS,
+                ADD_BUF  => true
+                )
+            port map (
+                clk     => system_clk,
+                rd_en   => do_read,
+                rd_addr => rd_addr,
+                rd_data => dout,
+                wr_sel  => wr_sel_m,
+                wr_addr => wr_addr,
+                wr_data => wr_data
+                );
+        process(all)
+        begin
+            --
+            -- Read port
+            --
+            do_read <= '1';
+            cache_out(i) <= dout;
+            rd_addr <= std_ulogic_vector(to_unsigned(req_row, ROW_BITS));
+
+            --
+            -- Write mux: cache refills from DRAM or writes from Wishbone
+            --
+            if state = IDLE then
+                -- Write from wishbone
+                wr_addr <= std_ulogic_vector(to_unsigned(req_row, ROW_BITS));
+                wr_data <= req_wdata;
+                wr_sel  <= req_we;
+            else
+                -- Refill from DRAM
+                wr_data <= user_port0_rdata_data;
+                wr_sel  <= (others => '1');
+                wr_addr <= std_ulogic_vector(to_unsigned(refill_row, ROW_BITS));
+            end if;
+
+            --
+            -- Write enable logic
+            --
+            do_write <= '0';
+            if req_op = OP_STORE_HIT and req_hit_way = i then
+                do_write <= '1';
+            elsif user_port0_rdata_valid = '1' and refill_way = i then
+                do_write <= '1';
+            end if;
+
+            -- Mask write selects with do_write since BRAM doesn't always
+            -- have a global write-enable (Vivado generates TDP instead
+            -- of SDP when using one, thus doubling cache BRAM usage).
+            for i in 0 to ROW_SIZE-1 loop
+                wr_sel_m(i) <= wr_sel(i) and do_write;
+            end loop;
+
+            if TRACE and rising_edge(system_clk) then
+                if do_write = '1' then
+                    report "cache write way:" & integer'image(i) &
+                        " addr:" & to_hstring(wr_addr) &
+                        " sel:" & to_hstring(wr_sel_m) &
+                        " data:" & to_hstring(wr_data);
+                end if;
+            end if;
+        end process;
+    end generate;
+
+    -- Generate PLRUs
+    maybe_plrus: if NUM_WAYS > 1 generate
+    begin
+        plrus: for i in 0 to NUM_LINES-1 generate
+            -- PLRU interface
+            signal plru_acc    : std_ulogic_vector(WAY_BITS-1 downto 0);
+            signal plru_acc_en : std_ulogic;
+            signal plru_out    : std_ulogic_vector(WAY_BITS-1 downto 0);
+        begin
+            plru : entity work.plru
+                generic map (
+                    BITS => WAY_BITS
+                    )
+                port map (
+                    clk => system_clk,
+                    rst => system_reset,
+                    acc => plru_acc,
+                    acc_en => plru_acc_en,
+                    lru => plru_out
+                    );
+
+            process(req_index, req_op, req_hit_way, plru_out)
+            begin
+                -- PLRU interface
+                if (req_op = OP_LOAD_HIT or
+                    req_op = OP_STORE_HIT) and req_index = i then
+                    plru_acc_en <= '1';
+                else
+                    plru_acc_en <= '0';
+                end if;
+                plru_acc <= std_ulogic_vector(to_unsigned(req_hit_way, WAY_BITS));
+                plru_victim(i) <= plru_out;
+            end process;
+        end generate;
+    end generate;
+
+    --
+    -- Wishbone interface:
+    --
+    --  - Incoming wishbone request latch (to help with timing)
+    --  - Read response pipeline (to match BRAM output buffer delay)
+    --  - Stall generation
+    --
+    -- XXX TODO: Properly handle cyc drops before all acks are sent...
+    --
+    request_latch: process(system_clk)
+    begin
+        if rising_edge(system_clk) then
+            -- We can latch a new request if we are idle (for now). We also
+            -- latch the absence of request. This is a pipeline that takes
+            -- one per-cycle unless non-IDLE.
+            --
+            if wb_out.stall = '0' then
+                -- Avoid constantly updating addr/data for unrelated requests
+                if wb_in.cyc = '1' then
+                    wb_req <= wb_in;
+                else
+                    wb_req.cyc <= wb_in.cyc;
+                    wb_req.stb <= wb_in.stb;
+                end if;
+
+                if TRACE then
+                    if wb_in.cyc = '1' and wb_in.stb = '1' then
+                        report "latch new wb req ! addr:" & to_hstring(wb_in.adr) &
+                            " we:" & std_ulogic'image(wb_in.we) &
+                            " sel:" & to_hstring(wb_in.sel);
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    --
+    --
+    -- Read response pipeline
+    --
+    -- XXX Might have to put store acks in there too (see comment in wb_response)
+    read_pipe: process(system_clk)
+    begin
+        if rising_edge(system_clk) then
+            read_ack_0 <= '1' when req_op = OP_LOAD_HIT else '0';
+            read_ad3_0 <= req_ad3;
+            read_way_0 <= req_hit_way;
+
+            read_ack_1 <= read_ack_0;
+            read_ad3_1 <= read_ad3_0;
+            read_way_1 <= read_way_0;
+
+            if TRACE then
+                if req_op = OP_LOAD_HIT then
+                    report "Load hit addr:" & to_hstring(wb_req.adr) &
+                        " idx:" & integer'image(req_index) &
+                        " tag:" & to_hstring(req_tag) &
+                        " way:" & integer'image(req_hit_way);
+                elsif req_op = OP_LOAD_MISS then
+                    report "Load miss addr:" & to_hstring(wb_req.adr);
+                end if;
+                if read_ack_0 = '1' then
+                    report "read data:" & to_hstring(cache_out(read_way_0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    wb_reponse: process(all)
+        variable rdata      : std_ulogic_vector(DRAM_DBITS-1 downto 0);
+        variable store_done : std_ulogic;
+    begin
+        -- Can we accept a store ? This is set when IDLE and the store
+        -- queue & command queue are not full.
+        --
+        -- Note: This is only used to control the WB request latch, stall
+        -- and store "early complete". We don't want to use this to control
+        -- cmd_valid to DRAM as this would create a circular dependency inside
+        -- LiteDRAM as cmd_ready I think is driven from cmd_valid.
+        --
+        -- The state machine that controls the command queue must thus
+        -- reproduce this logic at least partially.
+        --
+        -- Note also that user_port0_cmd_ready from LiteDRAM is combinational
+        -- from user_port0_cmd_valid. IE. we won't know that LiteDRAM cannot
+        -- accept a command until we try to send one.
+        --
+        if state = IDLE then
+            accept_store <= user_port0_cmd_ready and storeq_wr_ready;
+
+            -- Corner case !!! The read acks pipeline takes two extra cycles
+            -- which means a store ack can collide with a previous load hit
+            -- ack. Thus we stall stores if we have a load ack pending.
+            if read_ack_0 = '1' or read_ack_1 = '1' then
+                accept_store <= '0';
+            end if;
+        else
+            accept_store <= '0';
+        end if;
+
+        -- Generate stalls. For loads, we stall if we are going to take a load
+        -- miss or are in the middle of a refill. For stores, if we can't
+        -- accept it.
+        case state is
+        when IDLE =>
+            case req_op is
+            when OP_LOAD_MISS =>
+                wb_out.stall <= '1';
+            when OP_STORE_MISS | OP_STORE_HIT =>
+                wb_out.stall <= not accept_store;
+            when others =>
+                wb_out.stall <= '0';
+            end case;
+        when REFILL_WAIT_ACK =>
+            wb_out.stall <= '1';
+        end case;
+        
+        -- Data out mux
+        rdata := cache_out(read_way_1);
+        wb_out.dat <= rdata(127 downto 64) when read_ad3_1 = '1' else rdata(63 downto 0);
+
+        -- Early-complete stores on wishbone.
+        if req_op = OP_STORE_HIT or req_op = OP_STORE_MISS then
+            store_done := accept_store;
+        else
+            store_done := '0';
+        end if;
+
+        -- Generate ACKs on read hits and store complete
+        --
+        -- XXXX TODO: This can happen on store right behind loads !
+        -- This probably need to be fixed by putting store acks in
+        -- the same pipeline as the read acks. TOOD: Create a testbench
+        -- to exercise those corner cases as the core can't yet.
+        --
+        wb_out.ack <= read_ack_1 or store_done;
+        assert read_ack_0 = '0' or store_done = '0' report
+            "Read ack and store ack collision !"
+            severity failure;
+    end process;
+
+    --
+    -- Cache request decode
+    --
+    request_decode: process(all)
+        variable valid   : std_ulogic;
+        variable is_hit  : std_ulogic;
+        variable hit_way : way_t;
+    begin
+        -- Extract line, row and tag from request
+        req_index <= get_index(wb_req.adr);
+        req_row <= get_row(wb_req.adr(REAL_ADDR_BITS-1 downto 0));
+        req_tag <= get_tag(wb_req.adr);
+
+        -- Calculate address of beginning of cache line, will be
+        -- used for cache miss processing if needed
+        req_laddr <= wb_req.adr(REAL_ADDR_BITS - 1 downto LINE_OFF_BITS) &
+                     (LINE_OFF_BITS-1 downto 0 => '0');
+
+
+        -- Do we have a valid request in the WB latch ?
+        if state = IDLE then
+            valid := wb_req.cyc and wb_req.stb;
+        else
+            valid := '0';
+        end if;
+
+        -- Store signals
+        req_ad3      <= wb_req.adr(3);
+        req_wdata    <= wb_req.dat & wb_req.dat;
+        req_we       <= wb_req.sel & "00000000" when req_ad3 = '1' else
+                        "00000000" & wb_req.sel;
+
+        -- Test if pending request is a hit on any way
+        hit_way := 0;
+        is_hit := '0';
+        for i in way_t loop
+            if valid = '1' and cache_valids(req_index)(i) = '1' then
+                if read_tag(i, cache_tags(req_index)) = req_tag then
+                    hit_way := i;
+                    is_hit := '1';
+                end if;
+            end if;
+        end loop;
+
+        -- Generate the req op. We only allow OP_LOAD_* when in the
+        -- IDLE state as our PLRU and ACK generation rely on this,
+        -- stores are allowed in IDLE state.
+        --
+        req_op <= OP_NONE;
+        if valid = '1' then
+            if wb_req.we = '1' then
+                if is_hit = '1' then
+                    req_op <= OP_STORE_HIT;
+                else
+                    req_op <= OP_STORE_MISS;
+                end if;
+            else
+                if is_hit = '1' then
+                    req_op <= OP_LOAD_HIT;
+                else
+                    req_op <= OP_LOAD_MISS;
+                end if;
+            end if;
+        end if;
+        req_hit_way <= hit_way;
+   end process;
+
+    --
+    -- Store queue
+    --
+    -- For now, queue up to 16 stores
+    store_queue: entity work.sync_fifo
+	generic map (
+	    DEPTH => STOREQ_DEPTH,
+	    WIDTH => STOREQ_BITS
+	    )
+        port map (
+            clk      => system_clk,
+            reset    => system_reset,
+            rd_ready => storeq_rd_ready,
+            rd_valid => storeq_rd_valid,
+            rd_data  => storeq_rd_data,
+            wr_ready => storeq_wr_ready,
+            wr_valid => storeq_wr_valid,
+            wr_data  => storeq_wr_data
+            );
+
+    storeq_control : process(all)
+        variable stq_data : wishbone_data_type;
+        variable stq_sel  : std_ulogic_vector(DRAM_SBITS-1 downto 0);
+    begin
+        storeq_wr_data <= wb_req.dat & req_we;
+
+        -- Only accept store if we can send a command
+        if req_op = OP_STORE_HIT or req_op = OP_STORE_MISS then
+            storeq_wr_valid <= user_port0_cmd_ready;
+        else
+            storeq_wr_valid <= '0';
+        end if;
+
+        stq_data := storeq_rd_data(storeq_rd_data'left downto DRAM_SBITS);
+        stq_sel  := storeq_rd_data(DRAM_SBITS-1 downto 0);
+        user_port0_wdata_data  <= stq_data & stq_data;
+        user_port0_wdata_we    <= stq_sel;
+        user_port0_wdata_valid <= storeq_rd_valid;
+        storeq_rd_ready        <= user_port0_wdata_ready;
+
+        if TRACE then
+            if rising_edge(system_clk) then
+                if req_op = OP_STORE_HIT then
+                    report "Store hit to:" &
+                        to_hstring(wb_req.adr(DRAM_ABITS+3 downto 0)) &
+                        " data:" & to_hstring(req_wdata) &
+                        " we:" & to_hstring(req_we) &
+                        " V:" & std_ulogic'image(accept_store);
+                else
+                    report "Store miss to:" &
+                        to_hstring(wb_req.adr(DRAM_ABITS+3 downto 0)) &
+                        " data:" & to_hstring(req_wdata) &
+                        " we:" & to_hstring(req_we) &
+                        " V:" & std_ulogic'image(accept_store);
+                end if;
+                if storeq_wr_valid = '1' and storeq_wr_ready = '1' then
+                    report "storeq push " & to_hstring(storeq_wr_data);
+                end if;
+                if storeq_rd_valid = '1' and storeq_rd_ready = '1' then
+                    report "storeq pop " & to_hstring(storeq_rd_data);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- LiteDRAM command mux
+    dram_commands: process(all)
+    begin
+        if state = IDLE and (req_op = OP_STORE_HIT or req_op = OP_STORE_MISS) then
+            -- For stores, forward signals directly. Only send command if
+            -- the FIFO can accept a store
+            user_port0_cmd_addr  <= wb_req.adr(DRAM_ABITS+3 downto 4);
+            user_port0_cmd_we    <= '1';
+            user_port0_cmd_valid <= storeq_wr_ready;
+        else
+            -- For loads, we route via a latch controlled by the refill machine
+            user_port0_cmd_addr  <= refill_cmd_addr;
+            user_port0_cmd_valid <= refill_cmd_valid;
+            user_port0_cmd_we    <= '0';
+        end if;
+        user_port0_rdata_ready <= '1'; -- Always 1
+    end process;
+
+    -- LiteDRAM refill machine
+    --
+    -- This handles the cache line refills
+    --
+    refill_machine : process(system_clk)
+        variable tagset      : cache_tags_set_t;
+        variable cmds_done   : boolean;
+        variable replace_way : way_t;
+        variable wait_qdrain : boolean;
+    begin
+        if rising_edge(system_clk) then
+            -- On reset, clear all valid bits to force misses
+            if system_reset = '1' then
+                for i in index_t loop
+                    cache_valids(i) <= (others => '0');
+                end loop;
+                state <= IDLE;
+                refill_cmd_valid <= '0';
+            else
+                -- Main state machine
+                case state is
+                when IDLE =>
+                    assert refill_cmd_valid = '0' report "refill cmd valid in IDLE state !"
+                        severity failure;
+
+                    -- If NO_LS_OVERLAP is set, disallow a load miss if the store
+                    -- queue still has data in it.
+                    wait_qdrain := false;
+                    if NO_LS_OVERLAP then
+                        wait_qdrain := storeq_rd_valid = '1';
+                    end if;
+
+                    -- We need to read a cache line
+                    if req_op = OP_LOAD_MISS and not wait_qdrain then
+                        -- Grab way to replace
+                        replace_way := to_integer(unsigned(plru_victim(req_index)));
+
+                        -- Force misses on that way while refilling that line
+                        cache_valids(req_index)(replace_way) <= '0';
+
+                        -- Store new tag in selected way
+                        for i in 0 to NUM_WAYS-1 loop
+                            if i = replace_way then
+                                tagset := cache_tags(req_index);
+                                write_tag(i, tagset, req_tag);
+                                cache_tags(req_index) <= tagset;
+                            end if;
+                        end loop;
+
+                        -- Keep track of our index and way for subsequent stores
+                        refill_index <= req_index;
+                        refill_way   <= replace_way;
+                        refill_row   <= get_row(req_laddr);
+
+                        -- Prep for first DRAM read
+                        --
+                        -- XXX TODO: We could start a cycle early here by using
+                        -- combo logic to generate the first command in
+                        -- "dram_commands". In fact, we could make refill_cmd_addr
+                        -- only contain the "counter" bits and wire it with the
+                        -- other bits from req_laddr.
+                        refill_cmd_addr    <= req_laddr(DRAM_ABITS+3 downto 4);
+                        refill_cmd_valid   <= '1';
+
+                        if TRACE then
+                            report "refill addr " & to_hstring(req_laddr);
+                        end if;
+
+                        -- Track that we had one request sent
+                        state <= REFILL_WAIT_ACK;
+                    end if;
+
+                when REFILL_WAIT_ACK =>
+                    -- Commands are all sent if user_port0_cmd_valid is 0
+                    cmds_done := refill_cmd_valid = '0';
+
+                    -- If we are still sending requests, was one accepted ?
+                    if user_port0_cmd_ready = '1' and not cmds_done then
+                        -- That was the last word ? We are done sending. Clear
+                        -- command valid and set cmds_done so we can handle an
+                        -- eventual last ack on the same cycle.
+                        --
+                        if TRACE then
+                            report "got refill cmd ack !";
+                        end if;
+                        if is_last_row_addr(refill_cmd_addr) then
+                            refill_cmd_valid <= '0';
+                            cmds_done := true;
+                            if TRACE then
+                                report "all refill cmds done !";
+                            end if;
+                        else
+                            -- Calculate the next row address
+                            refill_cmd_addr <= next_row_addr(refill_cmd_addr);
+                            if TRACE then
+                                report "refill addr " &
+                                    to_hstring(next_row_addr(refill_cmd_addr));
+                            end if;
+                        end if;
+                    end if;
+
+                    -- Incoming read data processing
+                    if user_port0_rdata_valid = '1' then
+                        if TRACE then
+                            report "got refill data ack !";
+                        end if;
+                        -- Check for completion
+                        if cmds_done and is_last_row(refill_row) then
+                            if TRACE then
+                                report "all refill data done !";
+                            end if;
+                            -- Cache line is now valid
+                            cache_valids(refill_index)(refill_way) <= '1';
+                            -- We are done
+                            state <= IDLE;
+                        end if;
+
+                        -- Increment store row counter
+                        refill_row <= next_row(refill_row);
+                    end if;
+                end case;
+            end if;
+        end if;
+    end process;
+
+    may_trace: if LITEDRAM_TRACE generate
+        component litedram_trace_stub
+        end component;
+    begin
+        litedram_trace: litedram_trace_stub;
+    end generate;
+    
+    litedram: litedram_core
+        port map(
+            clk => clk_in,
+            rst => rst,
+            pll_locked => pll_locked,
+            ddram_a => ddram_a,
+            ddram_ba => ddram_ba,
+            ddram_ras_n => ddram_ras_n,
+            ddram_cas_n => ddram_cas_n,
+            ddram_we_n => ddram_we_n,
+            ddram_cs_n => ddram_cs_n,
+            ddram_dm => ddram_dm,
+            ddram_dq => ddram_dq,
+            ddram_dqs_p => ddram_dqs_p,
+            ddram_dqs_n => ddram_dqs_n,
+            ddram_clk_p => ddram_clk_p,
+            ddram_clk_n => ddram_clk_n,
+            ddram_cke => ddram_cke,
+            ddram_odt => ddram_odt,
+            ddram_reset_n => ddram_reset_n,
+            init_done => init_done,
+            init_error => init_error,
+            user_clk => system_clk,
+            user_rst => system_reset,
+            wb_ctrl_adr => wb_ctrl_adr,
+            wb_ctrl_dat_w => wb_ctrl_dat_w,
+            wb_ctrl_dat_r => wb_ctrl_dat_r,
+            wb_ctrl_sel => wb_ctrl_sel,
+            wb_ctrl_cyc => wb_ctrl_cyc,
+            wb_ctrl_stb => wb_ctrl_stb,
+            wb_ctrl_ack => wb_ctrl_ack,
+            wb_ctrl_we => wb_ctrl_we,
+            wb_ctrl_cti => "000",
+            wb_ctrl_bte => "00",
+            wb_ctrl_err => open,
+            user_port_native_0_cmd_valid => user_port0_cmd_valid,
+            user_port_native_0_cmd_ready => user_port0_cmd_ready,
+            user_port_native_0_cmd_we => user_port0_cmd_we,
+            user_port_native_0_cmd_addr => user_port0_cmd_addr,
+            user_port_native_0_wdata_valid => user_port0_wdata_valid,
+            user_port_native_0_wdata_ready => user_port0_wdata_ready,
+            user_port_native_0_wdata_we => user_port0_wdata_we,
+            user_port_native_0_wdata_data => user_port0_wdata_data,
+            user_port_native_0_rdata_valid => user_port0_rdata_valid,
+            user_port_native_0_rdata_ready => user_port0_rdata_ready,
+            user_port_native_0_rdata_data => user_port0_rdata_data
+            );
+
+end architecture behaviour;
diff --git a/litedram/extras/wrapper-mw-init.vhdl b/litedram/extras/wrapper-mw-init.vhdl
deleted file mode 100644
index 6bd3636..0000000
--- a/litedram/extras/wrapper-mw-init.vhdl
+++ /dev/null
@@ -1,1039 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use std.textio.all;
-
-library work;
-use work.wishbone_types.all;
-use work.utils.all;
-use work.helpers.all;
-
-entity litedram_wrapper is
-    generic (
-	DRAM_ABITS     : positive;
-	DRAM_ALINES    : positive;
-
-        -- Pseudo-ROM payload
-        PAYLOAD_SIZE      : natural;    
-        PAYLOAD_FILE      : string;
-
-        -- L2 cache --
-
-        -- Line size in bytes
-        LINE_SIZE         : positive := 128;
-        -- Number of lines in a set
-        NUM_LINES         : positive := 32;
-        -- Number of ways
-        NUM_WAYS          : positive := 4;
-        -- Max number of stores in the queue
-        STOREQ_DEPTH      : positive := 8;
-        -- Don't send loads until all pending stores acked in litedram
-        NO_LS_OVERLAP     : boolean  := false;
-
-        -- Debug
-        LITEDRAM_TRACE    : boolean  := false;
-        TRACE             : boolean  := false
-        );
-    port(
-        -- LiteDRAM generates the system clock and reset
-        -- from the input clkin
-        clk_in          : in std_ulogic;
-        rst             : in std_ulogic;
-        system_clk      : out std_ulogic;
-        system_reset    : out std_ulogic;
-        core_alt_reset  : out std_ulogic;
-        pll_locked      : out std_ulogic;
-
-        -- Wishbone ports:
-        wb_in           : in wishbone_master_out;
-        wb_out          : out wishbone_slave_out;
-        wb_ctrl_in      : in wb_io_master_out;
-        wb_ctrl_out     : out wb_io_slave_out;
-        wb_ctrl_is_csr  : in std_ulogic;
-        wb_ctrl_is_init : in std_ulogic;
-
-        -- Init core serial debug
-        serial_tx     : out std_ulogic;
-        serial_rx     : in std_ulogic;
-
-        -- Misc
-        init_done     : out std_ulogic;
-        init_error    : out std_ulogic;
-
-        -- DRAM wires
-        ddram_a       : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
-        ddram_ba      : out std_ulogic_vector(2 downto 0);
-        ddram_ras_n   : out std_ulogic;
-        ddram_cas_n   : out std_ulogic;
-        ddram_we_n    : out std_ulogic;
-        ddram_cs_n    : out std_ulogic;
-        ddram_dm      : out std_ulogic_vector(1 downto 0);
-        ddram_dq      : inout std_ulogic_vector(15 downto 0);
-        ddram_dqs_p   : inout std_ulogic_vector(1 downto 0);
-        ddram_dqs_n   : inout std_ulogic_vector(1 downto 0);
-        ddram_clk_p   : out std_ulogic;
-        ddram_clk_n   : out std_ulogic;
-        ddram_cke     : out std_ulogic;
-        ddram_odt     : out std_ulogic;
-        ddram_reset_n : out std_ulogic
-        );
-end entity litedram_wrapper;
-
-architecture behaviour of litedram_wrapper is
-
-    component litedram_core port (
-        clk                            : in std_ulogic;
-        rst                            : in std_ulogic;
-        pll_locked                     : out std_ulogic;
-        ddram_a                        : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
-        ddram_ba                       : out std_ulogic_vector(2 downto 0);
-        ddram_ras_n                    : out std_ulogic;
-        ddram_cas_n                    : out std_ulogic;
-        ddram_we_n                     : out std_ulogic;
-        ddram_cs_n                     : out std_ulogic;
-        ddram_dm                       : out std_ulogic_vector(1 downto 0);
-        ddram_dq                       : inout std_ulogic_vector(15 downto 0);
-        ddram_dqs_p                    : inout std_ulogic_vector(1 downto 0);
-        ddram_dqs_n                    : inout std_ulogic_vector(1 downto 0);
-        ddram_clk_p                    : out std_ulogic;
-        ddram_clk_n                    : out std_ulogic;
-        ddram_cke                      : out std_ulogic;
-        ddram_odt                      : out std_ulogic;
-        ddram_reset_n                  : out std_ulogic;
-        init_done                      : out std_ulogic;
-        init_error                     : out std_ulogic;
-        user_clk                       : out std_ulogic;
-        user_rst                       : out std_ulogic;
-        wb_ctrl_adr                    : in std_ulogic_vector(29 downto 0);
-        wb_ctrl_dat_w                  : in std_ulogic_vector(31 downto 0);
-        wb_ctrl_dat_r                  : out std_ulogic_vector(31 downto 0);
-        wb_ctrl_sel                    : in std_ulogic_vector(3 downto 0);
-        wb_ctrl_cyc                    : in std_ulogic;
-        wb_ctrl_stb                    : in std_ulogic;
-        wb_ctrl_ack                    : out std_ulogic;
-        wb_ctrl_we                     : in std_ulogic;
-        wb_ctrl_cti                    : in std_ulogic_vector(2 downto 0);
-        wb_ctrl_bte                    : in std_ulogic_vector(1 downto 0);
-        wb_ctrl_err                    : out std_ulogic;
-        user_port_native_0_cmd_valid   : in std_ulogic;
-        user_port_native_0_cmd_ready   : out std_ulogic;
-        user_port_native_0_cmd_we      : in std_ulogic;
-        user_port_native_0_cmd_addr    : in std_ulogic_vector(DRAM_ABITS-1 downto 0);
-        user_port_native_0_wdata_valid : in std_ulogic;
-        user_port_native_0_wdata_ready : out std_ulogic;
-        user_port_native_0_wdata_we    : in std_ulogic_vector(15 downto 0);
-        user_port_native_0_wdata_data  : in std_ulogic_vector(127 downto 0);
-        user_port_native_0_rdata_valid : out std_ulogic;
-        user_port_native_0_rdata_ready : in std_ulogic;
-        user_port_native_0_rdata_data  : out std_ulogic_vector(127 downto 0)
-        );
-    end component;
-    
-    signal user_port0_cmd_valid         : std_ulogic;
-    signal user_port0_cmd_ready         : std_ulogic;
-    signal user_port0_cmd_we            : std_ulogic;
-    signal user_port0_cmd_addr          : std_ulogic_vector(DRAM_ABITS-1 downto 0);
-    signal user_port0_wdata_valid       : std_ulogic;
-    signal user_port0_wdata_ready       : std_ulogic;
-    signal user_port0_wdata_we          : std_ulogic_vector(15 downto 0);
-    signal user_port0_wdata_data        : std_ulogic_vector(127 downto 0);
-    signal user_port0_rdata_valid       : std_ulogic;
-    signal user_port0_rdata_ready       : std_ulogic;
-    signal user_port0_rdata_data        : std_ulogic_vector(127 downto 0);
-
-    signal wb_ctrl_adr                  : std_ulogic_vector(29 downto 0);
-    signal wb_ctrl_dat_w                : std_ulogic_vector(31 downto 0);
-    signal wb_ctrl_dat_r                : std_ulogic_vector(31 downto 0);
-    signal wb_ctrl_sel                  : std_ulogic_vector(3 downto 0);
-    signal wb_ctrl_cyc                  : std_ulogic := '0';
-    signal wb_ctrl_stb                  : std_ulogic;
-    signal wb_ctrl_ack                  : std_ulogic;
-    signal wb_ctrl_we                   : std_ulogic;
-
-    signal wb_init_in                   : wb_io_master_out;
-    signal wb_init_out                  : wb_io_slave_out;
-
-    -- DRAM data port width
-    constant DRAM_DBITS                 : natural := 128;
-    constant DRAM_SBITS                 : natural := (DRAM_DBITS / 8);
-
-    -- BRAM organisation: We never access more than wishbone_data_bits at
-    -- a time so to save resources we make the array only that wide, and
-    -- use consecutive indices for to make a cache "line"
-    --
-    -- ROW_SIZE is the width in bytes of the BRAM (based on litedram, so 128-bits)
-    constant ROW_SIZE      : natural := DRAM_DBITS / 8;
-    -- ROW_PER_LINE is the number of row (litedram transactions) in a line
-    constant ROW_PER_LINE  : natural := LINE_SIZE / ROW_SIZE;
-    -- BRAM_ROWS is the number of rows in BRAM needed to represent the full
-    -- dcache
-    constant BRAM_ROWS     : natural := NUM_LINES * ROW_PER_LINE;
-
-    -- Bit fields counts in the address
-
-    -- ROW_BITS is the number of bits to select a row
-    constant ROW_BITS      : natural := log2(BRAM_ROWS);
-    -- ROW_LINEBITS is the number of bits to select a row within a line
-    constant ROW_LINEBITS  : natural := log2(ROW_PER_LINE);
-    -- LINE_OFF_BITS is the number of bits for the offset in a cache line
-    constant LINE_OFF_BITS : natural := log2(LINE_SIZE);
-    -- ROW_OFF_BITS is the number of bits for the offset in a row
-    constant ROW_OFF_BITS  : natural := log2(ROW_SIZE);
-    -- REAL_ADDR_BITS is the number of real address bits that we store
-    constant REAL_ADDR_BITS : positive := DRAM_ABITS + ROW_OFF_BITS;
-    -- INDEX_BITS is the number if bits to select a cache line
-    constant INDEX_BITS    : natural := log2(NUM_LINES);
-    -- SET_SIZE_BITS is the log base 2 of the set size
-    constant SET_SIZE_BITS : natural := LINE_OFF_BITS + INDEX_BITS;
-    -- TAG_BITS is the number of bits of the tag part of the address
-    constant TAG_BITS      : natural := REAL_ADDR_BITS - SET_SIZE_BITS;
-    -- WAY_BITS is the number of bits to select a way
-    constant WAY_BITS     : natural := log2(NUM_WAYS);
-
-    subtype row_t is integer range 0 to BRAM_ROWS-1;
-    subtype index_t is integer range 0 to NUM_LINES-1;
-    subtype way_t is integer range 0 to NUM_WAYS-1;
-
-    -- The cache data BRAM organized as described above for each way
-    subtype cache_row_t is std_ulogic_vector(DRAM_DBITS-1 downto 0);
-
-    -- The cache tags LUTRAM has a row per set. Vivado is a pain and will
-    -- not handle a clean (commented) definition of the cache tags as a 3d
-    -- memory. For now, work around it by putting all the tags
-    subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0);
---    type cache_tags_set_t is array(way_t) of cache_tag_t;
---    type cache_tags_array_t is array(index_t) of cache_tags_set_t;
-    constant TAG_RAM_WIDTH : natural := TAG_BITS * NUM_WAYS;
-    subtype cache_tags_set_t is std_logic_vector(TAG_RAM_WIDTH-1 downto 0);
-    type cache_tags_array_t is array(index_t) of cache_tags_set_t;
-
-    -- The cache valid bits
-    subtype cache_way_valids_t is std_ulogic_vector(NUM_WAYS-1 downto 0);
-    type cache_valids_t is array(index_t) of cache_way_valids_t;
-
-    -- Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
-    signal cache_tags   : cache_tags_array_t;
-    signal cache_valids : cache_valids_t;
-
-    attribute ram_style : string;
-    attribute ram_style of cache_tags : signal is "distributed";
-
-    --
-    -- Store queue signals
-    --
-    -- We store a single wishbone dword per entry (64-bit) but all
-    -- 16 sel bits for the DRAM.
-    -- XXX Investigate storing only AD3 and 8 sel bits if it's better
-    constant STOREQ_BITS  : positive := wishbone_data_bits + DRAM_SBITS;
-
-    signal storeq_rd_ready : std_ulogic;
-    signal storeq_rd_valid : std_ulogic;
-    signal storeq_rd_data  : std_ulogic_vector(STOREQ_BITS-1 downto 0);
-    signal storeq_wr_ready : std_ulogic;
-    signal storeq_wr_valid : std_ulogic;
-    signal storeq_wr_data  : std_ulogic_vector(STOREQ_BITS-1 downto 0);
-
-    --
-    -- Cache management signals
-    --
-
-     -- Cache state machine
-    type state_t is (IDLE,             -- Normal load hit processing
-                     REFILL_WAIT_ACK); -- Cache refill wait ack
-    signal state : state_t;
-
-    -- Latched WB request.
-    signal wb_req : wishbone_master_out := wishbone_master_out_init;
-
-    -- Read pipeline (to handle cache RAM latency)
-    signal read_ack_0  : std_ulogic;
-    signal read_ack_1  : std_ulogic;
-    signal read_ad3_0  : std_ulogic;
-    signal read_ad3_1  : std_ulogic;
-    signal read_way_0  : way_t;
-    signal read_way_1  : way_t;
-
-    -- Async signals decoding latched request
-    type req_op_t is (OP_NONE,
-                      OP_LOAD_HIT,
-                      OP_LOAD_MISS,
-                      OP_STORE_HIT,
-                      OP_STORE_MISS);
-
-    signal req_index    : index_t;
-    signal req_row      : row_t;
-    signal req_hit_way  : way_t;
-    signal req_tag      : cache_tag_t;
-    signal req_op       : req_op_t;
-    signal req_laddr    : std_ulogic_vector(REAL_ADDR_BITS-1 downto 0);
-    signal req_ad3      : std_ulogic;
-    signal req_we       : std_ulogic_vector(DRAM_SBITS-1 downto 0);
-    signal req_wdata    : std_ulogic_vector(DRAM_DBITS-1 downto 0);
-    signal accept_store : std_ulogic;
-
-    -- Line refill command signals and latches
-    signal refill_cmd_valid : std_ulogic;
-    signal refill_cmd_addr  : std_ulogic_vector(DRAM_ABITS-1 downto 0);
-    signal refill_way       : way_t;
-    signal refill_index     : index_t;
-    signal refill_row       : row_t;
-
-    -- Cache RAM interface
-    type cache_ram_out_t is array(way_t) of cache_row_t;
-    signal cache_out   : cache_ram_out_t;
-
-    -- PLRU output interface
-    type plru_out_t is array(index_t) of std_ulogic_vector(WAY_BITS-1 downto 0);
-    signal plru_victim : plru_out_t;
-
-    --
-    -- Helper functions to decode incoming requests
-    --
-
-    -- Return the cache line index (tag index) for an address
-    function get_index(addr: wishbone_addr_type) return index_t is
-    begin
-        return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto LINE_OFF_BITS)));
-    end;
-
-    -- Return the cache row index (data memory) for an address
-    function get_row(addr: std_ulogic_vector(REAL_ADDR_BITS-1 downto 0)) return row_t is
-    begin
-        return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto ROW_OFF_BITS)));
-    end;
-
-    -- Returns whether this is the last row of a line. It takes a DRAM address
-    function is_last_row_addr(addr: std_ulogic_vector(REAL_ADDR_BITS-1 downto ROW_OFF_BITS))
-        return boolean is
-        constant ones : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1');
-    begin
-        return addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS) = ones;
-    end;
-
-    -- Returns whether this is the last row of a line
-    function is_last_row(row: row_t) return boolean is
-        variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0);
-        constant ones  : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1');
-    begin
-        row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
-        return row_v(ROW_LINEBITS-1 downto 0) = ones;
-    end;
-
-    -- Return the address of the next row in the current cache line. It takes a
-    -- DRAM address
-    function next_row_addr(addr: std_ulogic_vector(REAL_ADDR_BITS-1 downto ROW_OFF_BITS))
-        return std_ulogic_vector is
-        variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
-        variable result  : std_ulogic_vector(REAL_ADDR_BITS-1 downto ROW_OFF_BITS);
-    begin
-        -- Is there no simpler way in VHDL to generate that 3 bits adder ?
-        row_idx := addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS);
-        row_idx := std_ulogic_vector(unsigned(row_idx) + 1);
-        result := addr;
-        result(LINE_OFF_BITS-1 downto ROW_OFF_BITS) := row_idx;
-        return result;
-    end;
-
-    -- Return the next row in the current cache line. We use a dedicated
-    -- function in order to limit the size of the generated adder to be
-    -- only the bits within a cache line (3 bits with default settings)
-    --
-    function next_row(row: row_t) return row_t is
-       variable row_v  : std_ulogic_vector(ROW_BITS-1 downto 0);
-       variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
-       variable result : std_ulogic_vector(ROW_BITS-1 downto 0);
-    begin
-       row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
-       row_idx := row_v(ROW_LINEBITS-1 downto 0);
-       row_v(ROW_LINEBITS-1 downto 0) := std_ulogic_vector(unsigned(row_idx) + 1);
-       return to_integer(unsigned(row_v));
-    end;
-
-    -- Get the tag value from the address
-    function get_tag(addr: wishbone_addr_type) return cache_tag_t is
-    begin
-        return addr(REAL_ADDR_BITS - 1 downto SET_SIZE_BITS);
-    end;
-
-    -- Read a tag from a tag memory row
-    function read_tag(way: way_t; tagset: cache_tags_set_t) return cache_tag_t is
-    begin
-        return tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS);
-    end;
-
-    -- Write a tag to tag memory row
-    procedure write_tag(way: in way_t; tagset: inout cache_tags_set_t;
-                        tag: cache_tag_t) is
-    begin
-        tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS) := tag;
-    end;
-
-begin
-
-    -- Sanity checks
-    assert LINE_SIZE mod ROW_SIZE = 0 report "LINE_SIZE not multiple of ROW_SIZE" severity FAILURE;
-    assert ispow2(LINE_SIZE)    report "LINE_SIZE not power of 2" severity FAILURE;
-    assert ispow2(NUM_LINES)    report "NUM_LINES not power of 2" severity FAILURE;
-    assert ispow2(ROW_PER_LINE) report "ROW_PER_LINE not power of 2" severity FAILURE;
-    assert (ROW_BITS = INDEX_BITS + ROW_LINEBITS)
-        report "geometry bits don't add up" severity FAILURE;
-    assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS)
-        report "geometry bits don't add up" severity FAILURE;
-    assert (REAL_ADDR_BITS = TAG_BITS + INDEX_BITS + LINE_OFF_BITS)
-        report "geometry bits don't add up" severity FAILURE;
-    assert (REAL_ADDR_BITS = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
-        report "geometry bits don't add up" severity FAILURE;
-    assert (128 = DRAM_DBITS)
-        report "Can't yet handle a DRAM width that isn't 128-bits" severity FAILURE;
-
-    -- alternate core reset address set when DRAM is not initialized.
-    core_alt_reset <= not init_done;
-
-    -- Init code BRAM memory slave 
-    init_ram_0: entity work.dram_init_mem
-        generic map(
-            EXTRA_PAYLOAD_FILE => PAYLOAD_FILE,
-            EXTRA_PAYLOAD_SIZE => PAYLOAD_SIZE
-            )
-        port map(
-            clk => system_clk,
-            wb_in => wb_init_in,
-            wb_out => wb_init_out
-            );
-
-    --
-    -- Control bus wishbone: This muxes the wishbone to the CSRs
-    -- and an internal small one to the init BRAM
-    --
-
-    -- Init DRAM wishbone IN signals
-    wb_init_in.adr <= wb_ctrl_in.adr;
-    wb_init_in.dat <= wb_ctrl_in.dat;
-    wb_init_in.sel <= wb_ctrl_in.sel;
-    wb_init_in.we  <= wb_ctrl_in.we;
-    wb_init_in.stb <= wb_ctrl_in.stb;
-    wb_init_in.cyc <= wb_ctrl_in.cyc and wb_ctrl_is_init;
-
-    -- DRAM CSR IN signals. Extra latch to help with timing
-    csr_latch: process(system_clk)
-    begin
-        if rising_edge(system_clk) then
-            if system_reset = '1' then
-                wb_ctrl_cyc <= '0';
-                wb_ctrl_stb <= '0';
-            else
-                -- XXX Maybe only update addr when cyc = '1' to save power ?
-                wb_ctrl_adr   <= x"0000" & wb_ctrl_in.adr(15 downto 2);
-                wb_ctrl_dat_w <= wb_ctrl_in.dat;
-                wb_ctrl_sel   <= wb_ctrl_in.sel;
-                wb_ctrl_we    <= wb_ctrl_in.we;
-                wb_ctrl_cyc   <= wb_ctrl_in.cyc and wb_ctrl_is_csr;
-                wb_ctrl_stb   <= wb_ctrl_in.stb and wb_ctrl_is_csr;
-
-                -- Clear stb on ack otherwise the memory will latch
-                -- the write twice which breaks levelling. On the next
-                -- cycle we will latch an updated stb that takes the
-                -- ack into account.
-                if wb_ctrl_ack = '1' then
-                    wb_ctrl_stb <= '0';
-                end if;
-            end if;
-        end if;
-    end process;
-
-    -- Ctrl bus wishbone OUT signals. XXX Consider adding latch on
-    -- CSR response to help timing
-    wb_ctrl_out.ack   <= wb_ctrl_ack when wb_ctrl_is_csr = '1'
-                         else wb_init_out.ack;
-    wb_ctrl_out.dat   <= wb_ctrl_dat_r when wb_ctrl_is_csr = '1'
-                         else wb_init_out.dat;
-    wb_ctrl_out.stall <= wb_init_out.stall when wb_ctrl_is_init else
-                         '0' when wb_ctrl_in.cyc = '0' else not wb_ctrl_ack;
-
-
-    -- Generate a cache RAM for each way
-    rams: for i in 0 to NUM_WAYS-1 generate
-        signal do_read  : std_ulogic;
-        signal do_write : std_ulogic;
-        signal rd_addr  : std_ulogic_vector(ROW_BITS-1 downto 0);
-        signal wr_addr  : std_ulogic_vector(ROW_BITS-1 downto 0);
-        signal wr_data  : std_ulogic_vector(DRAM_DBITS-1 downto 0);
-        signal wr_sel   : std_ulogic_vector(ROW_SIZE-1 downto 0);
-        signal wr_sel_m : std_ulogic_vector(ROW_SIZE-1 downto 0);
-        signal dout     : cache_row_t;
-   begin
-        way: entity work.cache_ram
-            generic map (
-                ROW_BITS => ROW_BITS,
-                WIDTH    => DRAM_DBITS,
-                ADD_BUF  => true
-                )
-            port map (
-                clk     => system_clk,
-                rd_en   => do_read,
-                rd_addr => rd_addr,
-                rd_data => dout,
-                wr_sel  => wr_sel_m,
-                wr_addr => wr_addr,
-                wr_data => wr_data
-                );
-        process(all)
-        begin
-            --
-            -- Read port
-            --
-            do_read <= '1';
-            cache_out(i) <= dout;
-            rd_addr <= std_ulogic_vector(to_unsigned(req_row, ROW_BITS));
-
-            --
-            -- Write mux: cache refills from DRAM or writes from Wishbone
-            --
-            if state = IDLE then
-                -- Write from wishbone
-                wr_addr <= std_ulogic_vector(to_unsigned(req_row, ROW_BITS));
-                wr_data <= req_wdata;
-                wr_sel  <= req_we;
-            else
-                -- Refill from DRAM
-                wr_data <= user_port0_rdata_data;
-                wr_sel  <= (others => '1');
-                wr_addr <= std_ulogic_vector(to_unsigned(refill_row, ROW_BITS));
-            end if;
-
-            --
-            -- Write enable logic
-            --
-            do_write <= '0';
-            if req_op = OP_STORE_HIT and req_hit_way = i then
-                do_write <= '1';
-            elsif user_port0_rdata_valid = '1' and refill_way = i then
-                do_write <= '1';
-            end if;
-
-            -- Mask write selects with do_write since BRAM doesn't always
-            -- have a global write-enable (Vivado generates TDP instead
-            -- of SDP when using one, thus doubling cache BRAM usage).
-            for i in 0 to ROW_SIZE-1 loop
-                wr_sel_m(i) <= wr_sel(i) and do_write;
-            end loop;
-
-            if TRACE and rising_edge(system_clk) then
-                if do_write = '1' then
-                    report "cache write way:" & integer'image(i) &
-                        " addr:" & to_hstring(wr_addr) &
-                        " sel:" & to_hstring(wr_sel_m) &
-                        " data:" & to_hstring(wr_data);
-                end if;
-            end if;
-        end process;
-    end generate;
-
-    -- Generate PLRUs
-    maybe_plrus: if NUM_WAYS > 1 generate
-    begin
-        plrus: for i in 0 to NUM_LINES-1 generate
-            -- PLRU interface
-            signal plru_acc    : std_ulogic_vector(WAY_BITS-1 downto 0);
-            signal plru_acc_en : std_ulogic;
-            signal plru_out    : std_ulogic_vector(WAY_BITS-1 downto 0);
-        begin
-            plru : entity work.plru
-                generic map (
-                    BITS => WAY_BITS
-                    )
-                port map (
-                    clk => system_clk,
-                    rst => system_reset,
-                    acc => plru_acc,
-                    acc_en => plru_acc_en,
-                    lru => plru_out
-                    );
-
-            process(req_index, req_op, req_hit_way, plru_out)
-            begin
-                -- PLRU interface
-                if (req_op = OP_LOAD_HIT or
-                    req_op = OP_STORE_HIT) and req_index = i then
-                    plru_acc_en <= '1';
-                else
-                    plru_acc_en <= '0';
-                end if;
-                plru_acc <= std_ulogic_vector(to_unsigned(req_hit_way, WAY_BITS));
-                plru_victim(i) <= plru_out;
-            end process;
-        end generate;
-    end generate;
-
-    --
-    -- Wishbone interface:
-    --
-    --  - Incoming wishbone request latch (to help with timing)
-    --  - Read response pipeline (to match BRAM output buffer delay)
-    --  - Stall generation
-    --
-    -- XXX TODO: Properly handle cyc drops before all acks are sent...
-    --
-    request_latch: process(system_clk)
-    begin
-        if rising_edge(system_clk) then
-            -- We can latch a new request if we are idle (for now). We also
-            -- latch the absence of request. This is a pipeline that takes
-            -- one per-cycle unless non-IDLE.
-            --
-            if wb_out.stall = '0' then
-                -- Avoid constantly updating addr/data for unrelated requests
-                if wb_in.cyc = '1' then
-                    wb_req <= wb_in;
-                else
-                    wb_req.cyc <= wb_in.cyc;
-                    wb_req.stb <= wb_in.stb;
-                end if;
-
-                if TRACE then
-                    if wb_in.cyc = '1' and wb_in.stb = '1' then
-                        report "latch new wb req ! addr:" & to_hstring(wb_in.adr) &
-                            " we:" & std_ulogic'image(wb_in.we) &
-                            " sel:" & to_hstring(wb_in.sel);
-                    end if;
-                end if;
-            end if;
-        end if;
-    end process;
-
-    --
-    --
-    -- Read response pipeline
-    --
-    -- XXX Might have to put store acks in there too (see comment in wb_response)
-    read_pipe: process(system_clk)
-    begin
-        if rising_edge(system_clk) then
-            read_ack_0 <= '1' when req_op = OP_LOAD_HIT else '0';
-            read_ad3_0 <= req_ad3;
-            read_way_0 <= req_hit_way;
-
-            read_ack_1 <= read_ack_0;
-            read_ad3_1 <= read_ad3_0;
-            read_way_1 <= read_way_0;
-
-            if TRACE then
-                if req_op = OP_LOAD_HIT then
-                    report "Load hit addr:" & to_hstring(wb_req.adr) &
-                        " idx:" & integer'image(req_index) &
-                        " tag:" & to_hstring(req_tag) &
-                        " way:" & integer'image(req_hit_way);
-                elsif req_op = OP_LOAD_MISS then
-                    report "Load miss addr:" & to_hstring(wb_req.adr);
-                end if;
-                if read_ack_0 = '1' then
-                    report "read data:" & to_hstring(cache_out(read_way_0));
-                end if;
-            end if;
-        end if;
-    end process;
-
-    wb_reponse: process(all)
-        variable rdata      : std_ulogic_vector(DRAM_DBITS-1 downto 0);
-        variable store_done : std_ulogic;
-    begin
-        -- Can we accept a store ? This is set when IDLE and the store
-        -- queue & command queue are not full.
-        --
-        -- Note: This is only used to control the WB request latch, stall
-        -- and store "early complete". We don't want to use this to control
-        -- cmd_valid to DRAM as this would create a circular dependency inside
-        -- LiteDRAM as cmd_ready I think is driven from cmd_valid.
-        --
-        -- The state machine that controls the command queue must thus
-        -- reproduce this logic at least partially.
-        --
-        -- Note also that user_port0_cmd_ready from LiteDRAM is combinational
-        -- from user_port0_cmd_valid. IE. we won't know that LiteDRAM cannot
-        -- accept a command until we try to send one.
-        --
-        if state = IDLE then
-            accept_store <= user_port0_cmd_ready and storeq_wr_ready;
-
-            -- Corner case !!! The read acks pipeline takes two extra cycles
-            -- which means a store ack can collide with a previous load hit
-            -- ack. Thus we stall stores if we have a load ack pending.
-            if read_ack_0 = '1' or read_ack_1 = '1' then
-                accept_store <= '0';
-            end if;
-        else
-            accept_store <= '0';
-        end if;
-
-        -- Generate stalls. For loads, we stall if we are going to take a load
-        -- miss or are in the middle of a refill. For stores, if we can't
-        -- accept it.
-        case state is
-        when IDLE =>
-            case req_op is
-            when OP_LOAD_MISS =>
-                wb_out.stall <= '1';
-            when OP_STORE_MISS | OP_STORE_HIT =>
-                wb_out.stall <= not accept_store;
-            when others =>
-                wb_out.stall <= '0';
-            end case;
-        when REFILL_WAIT_ACK =>
-            wb_out.stall <= '1';
-        end case;
-        
-        -- Data out mux
-        rdata := cache_out(read_way_1);
-        wb_out.dat <= rdata(127 downto 64) when read_ad3_1 = '1' else rdata(63 downto 0);
-
-        -- Early-complete stores on wishbone.
-        if req_op = OP_STORE_HIT or req_op = OP_STORE_MISS then
-            store_done := accept_store;
-        else
-            store_done := '0';
-        end if;
-
-        -- Generate ACKs on read hits and store complete
-        --
-        -- XXXX TODO: This can happen on store right behind loads !
-        -- This probably need to be fixed by putting store acks in
-        -- the same pipeline as the read acks. TOOD: Create a testbench
-        -- to exercise those corner cases as the core can't yet.
-        --
-        wb_out.ack <= read_ack_1 or store_done;
-        assert read_ack_0 = '0' or store_done = '0' report
-            "Read ack and store ack collision !"
-            severity failure;
-    end process;
-
-    --
-    -- Cache request decode
-    --
-    request_decode: process(all)
-        variable valid   : std_ulogic;
-        variable is_hit  : std_ulogic;
-        variable hit_way : way_t;
-    begin
-        -- Extract line, row and tag from request
-        req_index <= get_index(wb_req.adr);
-        req_row <= get_row(wb_req.adr(REAL_ADDR_BITS-1 downto 0));
-        req_tag <= get_tag(wb_req.adr);
-
-        -- Calculate address of beginning of cache line, will be
-        -- used for cache miss processing if needed
-        req_laddr <= wb_req.adr(REAL_ADDR_BITS - 1 downto LINE_OFF_BITS) &
-                     (LINE_OFF_BITS-1 downto 0 => '0');
-
-
-        -- Do we have a valid request in the WB latch ?
-        if state = IDLE then
-            valid := wb_req.cyc and wb_req.stb;
-        else
-            valid := '0';
-        end if;
-
-        -- Store signals
-        req_ad3      <= wb_req.adr(3);
-        req_wdata    <= wb_req.dat & wb_req.dat;
-        req_we       <= wb_req.sel & "00000000" when req_ad3 = '1' else
-                        "00000000" & wb_req.sel;
-
-        -- Test if pending request is a hit on any way
-        hit_way := 0;
-        is_hit := '0';
-        for i in way_t loop
-            if valid = '1' and cache_valids(req_index)(i) = '1' then
-                if read_tag(i, cache_tags(req_index)) = req_tag then
-                    hit_way := i;
-                    is_hit := '1';
-                end if;
-            end if;
-        end loop;
-
-        -- Generate the req op. We only allow OP_LOAD_* when in the
-        -- IDLE state as our PLRU and ACK generation rely on this,
-        -- stores are allowed in IDLE state.
-        --
-        req_op <= OP_NONE;
-        if valid = '1' then
-            if wb_req.we = '1' then
-                if is_hit = '1' then
-                    req_op <= OP_STORE_HIT;
-                else
-                    req_op <= OP_STORE_MISS;
-                end if;
-            else
-                if is_hit = '1' then
-                    req_op <= OP_LOAD_HIT;
-                else
-                    req_op <= OP_LOAD_MISS;
-                end if;
-            end if;
-        end if;
-        req_hit_way <= hit_way;
-   end process;
-
-    --
-    -- Store queue
-    --
-    -- For now, queue up to 16 stores
-    store_queue: entity work.sync_fifo
-	generic map (
-	    DEPTH => STOREQ_DEPTH,
-	    WIDTH => STOREQ_BITS
-	    )
-        port map (
-            clk      => system_clk,
-            reset    => system_reset,
-            rd_ready => storeq_rd_ready,
-            rd_valid => storeq_rd_valid,
-            rd_data  => storeq_rd_data,
-            wr_ready => storeq_wr_ready,
-            wr_valid => storeq_wr_valid,
-            wr_data  => storeq_wr_data
-            );
-
-    storeq_control : process(all)
-        variable stq_data : wishbone_data_type;
-        variable stq_sel  : std_ulogic_vector(DRAM_SBITS-1 downto 0);
-    begin
-        storeq_wr_data <= wb_req.dat & req_we;
-
-        -- Only accept store if we can send a command
-        if req_op = OP_STORE_HIT or req_op = OP_STORE_MISS then
-            storeq_wr_valid <= user_port0_cmd_ready;
-        else
-            storeq_wr_valid <= '0';
-        end if;
-
-        stq_data := storeq_rd_data(storeq_rd_data'left downto DRAM_SBITS);
-        stq_sel  := storeq_rd_data(DRAM_SBITS-1 downto 0);
-        user_port0_wdata_data  <= stq_data & stq_data;
-        user_port0_wdata_we    <= stq_sel;
-        user_port0_wdata_valid <= storeq_rd_valid;
-        storeq_rd_ready        <= user_port0_wdata_ready;
-
-        if TRACE then
-            if rising_edge(system_clk) then
-                if req_op = OP_STORE_HIT then
-                    report "Store hit to:" &
-                        to_hstring(wb_req.adr(DRAM_ABITS+3 downto 0)) &
-                        " data:" & to_hstring(req_wdata) &
-                        " we:" & to_hstring(req_we) &
-                        " V:" & std_ulogic'image(accept_store);
-                else
-                    report "Store miss to:" &
-                        to_hstring(wb_req.adr(DRAM_ABITS+3 downto 0)) &
-                        " data:" & to_hstring(req_wdata) &
-                        " we:" & to_hstring(req_we) &
-                        " V:" & std_ulogic'image(accept_store);
-                end if;
-                if storeq_wr_valid = '1' and storeq_wr_ready = '1' then
-                    report "storeq push " & to_hstring(storeq_wr_data);
-                end if;
-                if storeq_rd_valid = '1' and storeq_rd_ready = '1' then
-                    report "storeq pop " & to_hstring(storeq_rd_data);
-                end if;
-            end if;
-        end if;
-    end process;
-
-    -- LiteDRAM command mux
-    dram_commands: process(all)
-    begin
-        if state = IDLE and (req_op = OP_STORE_HIT or req_op = OP_STORE_MISS) then
-            -- For stores, forward signals directly. Only send command if
-            -- the FIFO can accept a store
-            user_port0_cmd_addr  <= wb_req.adr(DRAM_ABITS+3 downto 4);
-            user_port0_cmd_we    <= '1';
-            user_port0_cmd_valid <= storeq_wr_ready;
-        else
-            -- For loads, we route via a latch controlled by the refill machine
-            user_port0_cmd_addr  <= refill_cmd_addr;
-            user_port0_cmd_valid <= refill_cmd_valid;
-            user_port0_cmd_we    <= '0';
-        end if;
-        user_port0_rdata_ready <= '1'; -- Always 1
-    end process;
-
-    -- LiteDRAM refill machine
-    --
-    -- This handles the cache line refills
-    --
-    refill_machine : process(system_clk)
-        variable tagset      : cache_tags_set_t;
-        variable cmds_done   : boolean;
-        variable replace_way : way_t;
-        variable wait_qdrain : boolean;
-    begin
-        if rising_edge(system_clk) then
-            -- On reset, clear all valid bits to force misses
-            if system_reset = '1' then
-                for i in index_t loop
-                    cache_valids(i) <= (others => '0');
-                end loop;
-                state <= IDLE;
-                refill_cmd_valid <= '0';
-            else
-                -- Main state machine
-                case state is
-                when IDLE =>
-                    assert refill_cmd_valid = '0' report "refill cmd valid in IDLE state !"
-                        severity failure;
-
-                    -- If NO_LS_OVERLAP is set, disallow a load miss if the store
-                    -- queue still has data in it.
-                    wait_qdrain := false;
-                    if NO_LS_OVERLAP then
-                        wait_qdrain := storeq_rd_valid = '1';
-                    end if;
-
-                    -- We need to read a cache line
-                    if req_op = OP_LOAD_MISS and not wait_qdrain then
-                        -- Grab way to replace
-                        replace_way := to_integer(unsigned(plru_victim(req_index)));
-
-                        -- Force misses on that way while refilling that line
-                        cache_valids(req_index)(replace_way) <= '0';
-
-                        -- Store new tag in selected way
-                        for i in 0 to NUM_WAYS-1 loop
-                            if i = replace_way then
-                                tagset := cache_tags(req_index);
-                                write_tag(i, tagset, req_tag);
-                                cache_tags(req_index) <= tagset;
-                            end if;
-                        end loop;
-
-                        -- Keep track of our index and way for subsequent stores
-                        refill_index <= req_index;
-                        refill_way   <= replace_way;
-                        refill_row   <= get_row(req_laddr);
-
-                        -- Prep for first DRAM read
-                        --
-                        -- XXX TODO: We could start a cycle early here by using
-                        -- combo logic to generate the first command in
-                        -- "dram_commands". In fact, we could make refill_cmd_addr
-                        -- only contain the "counter" bits and wire it with the
-                        -- other bits from req_laddr.
-                        refill_cmd_addr    <= req_laddr(DRAM_ABITS+3 downto 4);
-                        refill_cmd_valid   <= '1';
-
-                        if TRACE then
-                            report "refill addr " & to_hstring(req_laddr);
-                        end if;
-
-                        -- Track that we had one request sent
-                        state <= REFILL_WAIT_ACK;
-                    end if;
-
-                when REFILL_WAIT_ACK =>
-                    -- Commands are all sent if user_port0_cmd_valid is 0
-                    cmds_done := refill_cmd_valid = '0';
-
-                    -- If we are still sending requests, was one accepted ?
-                    if user_port0_cmd_ready = '1' and not cmds_done then
-                        -- That was the last word ? We are done sending. Clear
-                        -- command valid and set cmds_done so we can handle an
-                        -- eventual last ack on the same cycle.
-                        --
-                        if TRACE then
-                            report "got refill cmd ack !";
-                        end if;
-                        if is_last_row_addr(refill_cmd_addr) then
-                            refill_cmd_valid <= '0';
-                            cmds_done := true;
-                            if TRACE then
-                                report "all refill cmds done !";
-                            end if;
-                        else
-                            -- Calculate the next row address
-                            refill_cmd_addr <= next_row_addr(refill_cmd_addr);
-                            if TRACE then
-                                report "refill addr " &
-                                    to_hstring(next_row_addr(refill_cmd_addr));
-                            end if;
-                        end if;
-                    end if;
-
-                    -- Incoming read data processing
-                    if user_port0_rdata_valid = '1' then
-                        if TRACE then
-                            report "got refill data ack !";
-                        end if;
-                        -- Check for completion
-                        if cmds_done and is_last_row(refill_row) then
-                            if TRACE then
-                                report "all refill data done !";
-                            end if;
-                            -- Cache line is now valid
-                            cache_valids(refill_index)(refill_way) <= '1';
-                            -- We are done
-                            state <= IDLE;
-                        end if;
-
-                        -- Increment store row counter
-                        refill_row <= next_row(refill_row);
-                    end if;
-                end case;
-            end if;
-        end if;
-    end process;
-
-    may_trace: if LITEDRAM_TRACE generate
-        component litedram_trace_stub
-        end component;
-    begin
-        litedram_trace: litedram_trace_stub;
-    end generate;
-    
-    litedram: litedram_core
-        port map(
-            clk => clk_in,
-            rst => rst,
-            pll_locked => pll_locked,
-            ddram_a => ddram_a,
-            ddram_ba => ddram_ba,
-            ddram_ras_n => ddram_ras_n,
-            ddram_cas_n => ddram_cas_n,
-            ddram_we_n => ddram_we_n,
-            ddram_cs_n => ddram_cs_n,
-            ddram_dm => ddram_dm,
-            ddram_dq => ddram_dq,
-            ddram_dqs_p => ddram_dqs_p,
-            ddram_dqs_n => ddram_dqs_n,
-            ddram_clk_p => ddram_clk_p,
-            ddram_clk_n => ddram_clk_n,
-            ddram_cke => ddram_cke,
-            ddram_odt => ddram_odt,
-            ddram_reset_n => ddram_reset_n,
-            init_done => init_done,
-            init_error => init_error,
-            user_clk => system_clk,
-            user_rst => system_reset,
-            wb_ctrl_adr => wb_ctrl_adr,
-            wb_ctrl_dat_w => wb_ctrl_dat_w,
-            wb_ctrl_dat_r => wb_ctrl_dat_r,
-            wb_ctrl_sel => wb_ctrl_sel,
-            wb_ctrl_cyc => wb_ctrl_cyc,
-            wb_ctrl_stb => wb_ctrl_stb,
-            wb_ctrl_ack => wb_ctrl_ack,
-            wb_ctrl_we => wb_ctrl_we,
-            wb_ctrl_cti => "000",
-            wb_ctrl_bte => "00",
-            wb_ctrl_err => open,
-            user_port_native_0_cmd_valid => user_port0_cmd_valid,
-            user_port_native_0_cmd_ready => user_port0_cmd_ready,
-            user_port_native_0_cmd_we => user_port0_cmd_we,
-            user_port_native_0_cmd_addr => user_port0_cmd_addr,
-            user_port_native_0_wdata_valid => user_port0_wdata_valid,
-            user_port_native_0_wdata_ready => user_port0_wdata_ready,
-            user_port_native_0_wdata_we => user_port0_wdata_we,
-            user_port_native_0_wdata_data => user_port0_wdata_data,
-            user_port_native_0_rdata_valid => user_port0_rdata_valid,
-            user_port_native_0_rdata_ready => user_port0_rdata_ready,
-            user_port_native_0_rdata_data => user_port0_rdata_data
-            );
-
-end architecture behaviour;
diff --git a/litedram/extras/wrapper-self-init.vhdl b/litedram/extras/wrapper-self-init.vhdl
deleted file mode 100644
index d57c99b..0000000
--- a/litedram/extras/wrapper-self-init.vhdl
+++ /dev/null
@@ -1,225 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use std.textio.all;
-
-library work;
-use work.wishbone_types.all;
-
-entity litedram_wrapper is
-    generic (
-	DRAM_ABITS     : positive;
-	DRAM_ALINES    : positive
-	);
-    port(
-	-- LiteDRAM generates the system clock and reset
-	-- from the input clkin
-	clk_in          : in std_ulogic;
-	rst             : in std_ulogic;
-	system_clk      : out std_ulogic;
-	system_reset    : out std_ulogic;
-	core_alt_reset  : out std_ulogic;
-	pll_locked      : out std_ulogic;
-
-	-- Wishbone ports:
-	wb_in           : in wishbone_master_out;
-	wb_out          : out wishbone_slave_out;
-	wb_ctrl_in      : in wb_io_master_out;
-	wb_ctrl_out     : out wb_io_slave_out;
-	wb_ctrl_is_csr  : in std_ulogic;
-	wb_ctrl_is_init : in std_ulogic;
-
-	-- Init core serial debug
-	serial_tx     : out std_ulogic;
-	serial_rx     : in std_ulogic;
-
-	-- Misc
-	init_done     : out std_ulogic;
-	init_error    : out std_ulogic;
-
-	-- DRAM wires
-	ddram_a       : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
-	ddram_ba      : out std_ulogic_vector(2 downto 0);
-	ddram_ras_n   : out std_ulogic;
-	ddram_cas_n   : out std_ulogic;
-	ddram_we_n    : out std_ulogic;
-	ddram_cs_n    : out std_ulogic;
-	ddram_dm      : out std_ulogic_vector(1 downto 0);
-	ddram_dq      : inout std_ulogic_vector(15 downto 0);
-	ddram_dqs_p   : inout std_ulogic_vector(1 downto 0);
-	ddram_dqs_n   : inout std_ulogic_vector(1 downto 0);
-	ddram_clk_p   : out std_ulogic;
-	ddram_clk_n   : out std_ulogic;
-	ddram_cke     : out std_ulogic;
-	ddram_odt     : out std_ulogic;
-	ddram_reset_n : out std_ulogic
-end entity litedram_wrapper;
-
-architecture behaviour of litedram_wrapper is
-
-    component litedram_core port (
-	clk                    : in std_ulogic;
-	rst                    : in std_ulogic;
-	serial_tx              : out std_ulogic;
-	serial_rx              : in std_ulogic;
-	pll_locked             : out std_ulogic;
-	ddram_a                : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
-	ddram_ba               : out std_ulogic_vector(2 downto 0);
-	ddram_ras_n            : out std_ulogic;
-	ddram_cas_n            : out std_ulogic;
-	ddram_we_n             : out std_ulogic;
-	ddram_cs_n             : out std_ulogic;
-	ddram_dm               : out std_ulogic_vector(1 downto 0);
-	ddram_dq               : inout std_ulogic_vector(15 downto 0);
-	ddram_dqs_p            : inout std_ulogic_vector(1 downto 0);
-	ddram_dqs_n            : inout std_ulogic_vector(1 downto 0);
-	ddram_clk_p            : out std_ulogic;
-	ddram_clk_n            : out std_ulogic;
-	ddram_cke              : out std_ulogic;
-	ddram_odt              : out std_ulogic;
-	ddram_reset_n          : out std_ulogic;
-	init_done              : out std_ulogic;
-	init_error             : out std_ulogic;
-	user_clk               : out std_ulogic;
-	user_rst               : out std_ulogic;
-	user_port_native_0_cmd_valid   : in std_ulogic;
-	user_port_native_0_cmd_ready   : out std_ulogic;
-	user_port_native_0_cmd_we      : in std_ulogic;
-	user_port_native_0_cmd_addr    : in std_ulogic_vector(DRAM_ABITS-1 downto 0);
-	user_port_native_0_wdata_valid : in std_ulogic;
-	user_port_native_0_wdata_ready : out std_ulogic;
-	user_port_native_0_wdata_we    : in std_ulogic_vector(15 downto 0);
-	user_port_native_0_wdata_data  : in std_ulogic_vector(127 downto 0);
-	user_port_native_0_rdata_valid : out std_ulogic;
-	user_port_native_0_rdata_ready : in std_ulogic;
-	user_port_native_0_rdata_data  : out std_ulogic_vector(127 downto 0)
-	);
-    end component;
-    
-    signal user_port0_cmd_valid		: std_ulogic;
-    signal user_port0_cmd_ready		: std_ulogic;
-    signal user_port0_cmd_we		: std_ulogic;
-    signal user_port0_cmd_addr		: std_ulogic_vector(DRAM_ABITS-1 downto 0);
-    signal user_port0_wdata_valid	: std_ulogic;
-    signal user_port0_wdata_ready	: std_ulogic;
-    signal user_port0_wdata_we		: std_ulogic_vector(15 downto 0);
-    signal user_port0_wdata_data	: std_ulogic_vector(127 downto 0);
-    signal user_port0_rdata_valid	: std_ulogic;
-    signal user_port0_rdata_ready	: std_ulogic;
-    signal user_port0_rdata_data	: std_ulogic_vector(127 downto 0);
-
-    signal ad3                          : std_ulogic;
-
-    signal dram_user_reset              : std_ulogic;
-
-    type state_t is (CMD, MWRITE, MREAD);
-    signal state : state_t;
-
-begin
-
-    -- Reset, lift it when init done, no alt core reset
-    system_reset <= dram_user_reset or not init_done;
-    core_alt_reset <= '0';
-
-    -- Control bus is unused
-    wb_ctrl_out.ack   <= (wb_is_ctrl = '1' or wb_is_init = '1') and wb_ctrl_in.cyc;
-                         else wb_init_out.ack;
-    wb_ctrl_out.dat   <= (others => '0');
-    wb_ctrl_out.stall <= '0';
-
-    --
-    -- Data bus wishbone to LiteDRAM native port
-    --
-    -- Address bit 3 selects the top or bottom half of the data
-    -- bus (64-bit wishbone vs. 128-bit DRAM interface)
-    --
-    -- XXX TODO: Figure out how to pipeline this
-    --
-    ad3 <= wb_in.adr(3);
-
-    -- Wishbone port IN signals
-    user_port0_cmd_valid   <= wb_in.cyc and wb_in.stb when state = CMD else '0';
-    user_port0_cmd_we      <= wb_in.we when state = CMD else '0';
-    user_port0_wdata_valid <= '1' when state = MWRITE else '0';
-    user_port0_rdata_ready <= '1' when state = MREAD else '0';
-    user_port0_cmd_addr    <= wb_in.adr(DRAM_ABITS+3 downto 4);
-    user_port0_wdata_data  <= wb_in.dat & wb_in.dat;
-    user_port0_wdata_we    <= wb_in.sel & "00000000" when ad3 = '1' else
-                              "00000000" & wb_in.sel;
-
-    -- Wishbone OUT signals
-    wb_out.ack <= user_port0_wdata_ready when state = MWRITE else
-		  user_port0_rdata_valid when state = MREAD else '0';
-
-    wb_out.dat <= user_port0_rdata_data(127 downto 64) when ad3 = '1' else
-		  user_port0_rdata_data(63 downto 0);
-
-    -- We don't do pipelining yet.
-    wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack;
-
-    -- DRAM user port State machine
-    sm: process(system_clk)
-    begin
-	
-	if rising_edge(system_clk) then
-	    if dram_user_reset = '1' then
-		state <= CMD;
-	    else
-		case state is
-		when CMD =>
-		    if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then
-			state <= MWRITE when wb_in.we = '1' else MREAD;
-		    end if;
-		when MWRITE =>
-		    if user_port0_wdata_ready = '1' then
-			state <= CMD;
-		    end if;
-		when MREAD =>
-		    if user_port0_rdata_valid = '1' then
-			state <= CMD;
-		    end if;
-		end case;
-	    end if;
-	end if;
-    end process;
-
-    litedram: litedram_core
-	port map(
-	    clk => clk_in,
-	    rst => rst,
-	    serial_tx => serial_tx,
-	    serial_rx => serial_rx,
-	    pll_locked => pll_locked,
-	    ddram_a => ddram_a,
-	    ddram_ba => ddram_ba,
-	    ddram_ras_n => ddram_ras_n,
-	    ddram_cas_n => ddram_cas_n,
-	    ddram_we_n => ddram_we_n,
-	    ddram_cs_n => ddram_cs_n,
-	    ddram_dm => ddram_dm,
-	    ddram_dq => ddram_dq,
-	    ddram_dqs_p => ddram_dqs_p,
-	    ddram_dqs_n => ddram_dqs_n,
-	    ddram_clk_p => ddram_clk_p,
-	    ddram_clk_n => ddram_clk_n,
-	    ddram_cke => ddram_cke,
-	    ddram_odt => ddram_odt,
-	    ddram_reset_n => ddram_reset_n,
-	    init_done => init_done,
-	    init_error => init_error,
-	    user_clk => system_clk,
-	    user_rst => dram_user_reset,
-	    user_port_native_0_cmd_valid => user_port0_cmd_valid,
-	    user_port_native_0_cmd_ready => user_port0_cmd_ready,
-	    user_port_native_0_cmd_we => user_port0_cmd_we,
-	    user_port_native_0_cmd_addr => user_port0_cmd_addr,
-	    user_port_native_0_wdata_valid => user_port0_wdata_valid,
-	    user_port_native_0_wdata_ready => user_port0_wdata_ready,
-	    user_port_native_0_wdata_we => user_port0_wdata_we,
-	    user_port_native_0_wdata_data => user_port0_wdata_data,
-	    user_port_native_0_rdata_valid => user_port0_rdata_valid,
-	    user_port_native_0_rdata_ready => user_port0_rdata_ready,
-	    user_port_native_0_rdata_data => user_port0_rdata_data
-	    );
-
-end architecture behaviour;
diff --git a/litedram/gen-src/arty.yml b/litedram/gen-src/arty.yml
index 40211f0..4472d56 100644
--- a/litedram/gen-src/arty.yml
+++ b/litedram/gen-src/arty.yml
@@ -3,8 +3,8 @@
 
 {
     # General ------------------------------------------------------------------
-    "cpu":        "vexriscv",  # Type of CPU used for init/calib (vexriscv, lm32)
-    "cpu_variant":"minimal",
+    "cpu":        "None",  # Type of CPU used for init/calib (vexriscv, lm32)
+    "cpu_variant":"standard",
     "speedgrade": -1,          # FPGA speedgrade
     "memtype":    "DDR3",      # DRAM type
 
@@ -37,6 +37,6 @@
     },
 
     # CSR Port -----------------------------------------------------------------
-    "csr_base"  : 0xc0100000, # For cpu=None only
-    csr_data_width : 32,
+    "csr_alignment"  : 32,
+    "csr_data_width" : 32,
 }
diff --git a/litedram/gen-src/generate.py b/litedram/gen-src/generate.py
index 7dcfc4e..15cd846 100755
--- a/litedram/gen-src/generate.py
+++ b/litedram/gen-src/generate.py
@@ -74,7 +74,7 @@ def build_init_code(build_dir, is_sim):
 
     return os.path.join(sw_dir, "obj", "sdram_init.hex")
 
-def generate_one(t, mw_init):
+def generate_one(t):
 
     print("Generating target:", t)
 
@@ -106,12 +106,6 @@ def generate_one(t, mw_init):
         if k == "sdram_phy":
             core_config[k] = getattr(litedram_phys, core_config[k])
 
-    # Override values for mw_init
-    if mw_init:
-        core_config["cpu"] = None
-        core_config["cpu_variant"] = "standard"
-        core_config["csr_alignment"] = 64
-
     # Generate core
     if is_sim:
         platform = SimPlatform("", io=[])
@@ -131,24 +125,15 @@ def generate_one(t, mw_init):
     # Grab generated gatewar dir
     gw_dir = os.path.join(build_dir, "gateware")
 
-    # Generate init-cpu.txt and generate init code
-    cpu = core_config["cpu"]
-    if mw_init:
-        write_to_file(os.path.join(t_dir, "init-cpu.txt"), "none")
-        src_init_file = build_init_code(build_dir, is_sim)
-        src_initram_file = os.path.join(gen_src_dir, "dram-init-mem.vhdl")
-    else:
-        write_to_file(os.path.join(t_dir, "init-cpu.txt"), cpu)
-        src_init_file = os.path.join(gw_dir, "mem.init")
-        src_initram_file = os.path.join(gen_src_dir, "no-init-mem.vhdl")
+    # Generate init code
+    src_init_file = build_init_code(build_dir, is_sim)
+    src_initram_file = os.path.join(gen_src_dir, "dram-init-mem.vhdl")
 
     # Copy generated files to target dir, amend them if necessary
     initfile_name = "litedram_core.init"
     core_file = os.path.join(gw_dir, "litedram_core.v")
     dst_init_file = os.path.join(t_dir, initfile_name)
     dst_initram_file = os.path.join(t_dir, "litedram-initmem.vhdl")
-    if not mw_init:
-        replace_in_file(core_file, "mem.init", initfile_name)
     shutil.copyfile(src_init_file, dst_init_file)    
     shutil.copyfile(src_initram_file, dst_initram_file)
     if is_sim:
@@ -159,13 +144,8 @@ def generate_one(t, mw_init):
 def main():
 
     targets = ['arty','nexys-video', 'sim']
-#    targets = ['sim']
-
-    # XXX Set mw_init to False to use a local VexRiscV for memory inits
     for t in targets:
-        generate_one(t, mw_init = True)
-
-    # XXX TODO: Remove build dir unless told not to via cmdline option
+        generate_one(t)
     
 if __name__ == "__main__":
     main()
diff --git a/litedram/gen-src/nexys-video.yml b/litedram/gen-src/nexys-video.yml
index f9f8f09..287f2f2 100644
--- a/litedram/gen-src/nexys-video.yml
+++ b/litedram/gen-src/nexys-video.yml
@@ -3,8 +3,8 @@
 
 {
     # General ------------------------------------------------------------------
-    "cpu":        "vexriscv",  # Type of CPU used for init/calib (vexriscv, lm32)
-    "cpu_variant":"minimal",
+    "cpu":        "None",  # Type of CPU used for init/calib (vexriscv, lm32)
+    "cpu_variant":"standard",
     "speedgrade": -1,          # FPGA speedgrade
     "memtype":    "DDR3",      # DRAM type
 
@@ -37,6 +37,6 @@
     },
 
     # CSR Port -----------------------------------------------------------------
-    "csr_base"  : 0xc0100000, # For cpu=None only
-    csr_data_width : 32,
+    "csr_alignment"  : 32,
+    "csr_data_width" : 32,
 }
diff --git a/litedram/gen-src/sim.yml b/litedram/gen-src/sim.yml
index afb0638..0160000 100644
--- a/litedram/gen-src/sim.yml
+++ b/litedram/gen-src/sim.yml
@@ -4,10 +4,10 @@
 {
     # General ------------------------------------------------------------------
     "cpu":        "None",  # Type of CPU used for init/calib (vexriscv, lm32)
-    "cpu_variant":"minimal",
+    "cpu_variant":"standard",
     "speedgrade": -1,          # FPGA speedgrade
     "memtype":    "DDR3",      # DRAM type
-     "sim" : "True",
+    "sim" : "True",
 
     # PHY ----------------------------------------------------------------------
     "cmd_delay":       0,             # Command additional delay (in taps)
@@ -36,4 +36,8 @@
             "type": "native",
         },
     },
+
+    # CSR Port -----------------------------------------------------------------
+    "csr_alignment"  : 32,
+    "csr_data_width" : 32,
 }
diff --git a/litedram/generated/arty/init-cpu.txt b/litedram/generated/arty/init-cpu.txt
deleted file mode 100644
index c86c3f3..0000000
--- a/litedram/generated/arty/init-cpu.txt
+++ /dev/null
@@ -1 +0,0 @@
-none
\ No newline at end of file
diff --git a/litedram/generated/arty/litedram_core.v b/litedram/generated/arty/litedram_core.v
index a43ca24..dc4a031 100644
--- a/litedram/generated/arty/litedram_core.v
+++ b/litedram/generated/arty/litedram_core.v
@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-02 11:27:36
+// Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-05 11:21:51
 //--------------------------------------------------------------------------------
 module litedram_core(
 	input wire clk,
diff --git a/litedram/generated/nexys-video/init-cpu.txt b/litedram/generated/nexys-video/init-cpu.txt
deleted file mode 100644
index c86c3f3..0000000
--- a/litedram/generated/nexys-video/init-cpu.txt
+++ /dev/null
@@ -1 +0,0 @@
-none
\ No newline at end of file
diff --git a/litedram/generated/nexys-video/litedram_core.v b/litedram/generated/nexys-video/litedram_core.v
index c1ff475..e135402 100644
--- a/litedram/generated/nexys-video/litedram_core.v
+++ b/litedram/generated/nexys-video/litedram_core.v
@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-02 11:27:37
+// Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-05 11:21:52
 //--------------------------------------------------------------------------------
 module litedram_core(
 	input wire clk,
diff --git a/litedram/generated/sim/init-cpu.txt b/litedram/generated/sim/init-cpu.txt
deleted file mode 100644
index c86c3f3..0000000
--- a/litedram/generated/sim/init-cpu.txt
+++ /dev/null
@@ -1 +0,0 @@
-none
\ No newline at end of file
diff --git a/litedram/generated/sim/litedram_core.init b/litedram/generated/sim/litedram_core.init
index 5dd2a84..bfc17ca 100644
--- a/litedram/generated/sim/litedram_core.init
+++ b/litedram/generated/sim/litedram_core.init
@@ -519,11 +519,11 @@ f8c101a838800140
 38c101987c651b78
 7fe3fb78f8e101b0
 f92101c0f90101b8
-48000d1df94101c8
+48000cfdf94101c8
 7c7e1b7860000000
-480008357fe3fb78
+480008157fe3fb78
 3821017060000000
-480012dc7fc3f378
+480012bc7fc3f378
 0100000000000000
 4e80002000000280
 0000000000000000
@@ -534,256 +534,252 @@ f92101c0f90101b8
 7c0802a63842955c
 7d800026fbe1fff8
 91810008f8010010
-48000729f821ff91
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 3c62ffff60000000
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 548400023880ffff
 7c8026ea7c0004ac
 3fe0c0003c62ffff
-63ff000838637d80
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 3c62ffff4bffff11
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 7c0004ac4bffff01
 73e900017fe0feea
 3c62ffff41820010
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 4d80000073e90002
 3c62ffff41820010
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 4e00000073e90004
 3c62ffff41820010
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 4bfffea57fe3fb78
 3c80c00041920028
 7884002060840010
 7c8026ea7c0004ac
 7884b2823c62ffff
-4bfffe7d38637dd0
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 3c80c000418e004c
 7884002060840018
 7c8026ea7c0004ac
 788465023c62ffff
-4bfffe5538637df0
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 608400303c80c000
 7c0004ac78840020
 3c62ffff7c8026ea
-38637e107884b282
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 3d20c0004bfffe31
 7929002061290020
 7d204eea7c0004ac
 3c62ffff3c80000f
-38637e3060844240
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 4bfffe057c892392
 4bfffdfd7fe3fb78
 3ca2ffff418e0028
 3c62ffff3c82ffff
-38847e6038a57e50
-4bfffddd38637e68
-6000000048000455
+38847e4038a57e30
+4bfffddd38637e48
+6000000048000419
 3c62ffff41920020
-4bfffdc538637e98
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 8181000838210070
-480010f87d818120
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 3c80f0004bfffda9
 6084400038a0ffff
 7884002054a50422
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 3c62ffff60000000
-4bfffd7d38637ed0
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 e801001038210070
 ebe1fff881810008
 7d8181207c0803a6
 000000004bfffde4
 0000018003000000
-7869c0223d40c010
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 7c0004ac79290020
-4e8000207c604f2a
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 0000000000000000
-3d20c01000000000
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-392000013d40c010
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+3c4c000100000000
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 7d20572a7c0004ac
-000000004e800020
-0000000000000000
-384292d03c4c0001
-3d40c0107c0802a6
-39200001614a0800
-f8010010794a0020
-7c0004acf821ffa1
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-000000004e800020
-0000008001000000
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 4200fff839290004
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 3d2040007d4903a6
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 3900010060000000
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 7d2942787d293838
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 4082001c2c230000
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-7fa0e72a7c0004ac
+7f80df2a7c0004ac
+7f80d72a7c0004ac
+48000b6038210090
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 4bffffec38600001
 0100000000000000
-3c4c000100000580
-3d20c00038428e1c
+3c4c000100000680
+3d20c00038428e3c
 6129200060000000
-f922803079290020
+f922801079290020
 612900203d20c000
 7c0004ac79290020
 3d40001c7d204eea
 7d295392614a2000
-394a0018e9428030
+394a0018e9428010
 7c0004ac3929ffff
 4e8000207d2057ea
 0000000000000000
 3c4c000100000000
-6000000038428dbc
-39290010e9228030
+6000000038428ddc
+39290010e9228010
 7d204eea7c0004ac
 4082ffe871290008
-e94280305469063e
+e94280105469063e
 7d2057ea7c0004ac
 000000004e800020
 0000000000000000
-38428d783c4c0001
+38428d983c4c0001
 fbc1fff07c0802a6
 3bc3fffffbe1fff8
 f821ffd1f8010010
@@ -857,7 +853,7 @@ f924000039290002
 7c6307b43863ffe0
 000000004e800020
 0000000000000000
-38428b283c4c0001
+38428b483c4c0001
 3d2037367c0802a6
 612935347d908026
 65293332792907c6
@@ -891,7 +887,7 @@ fbfd00007fe9fa14
 4bfffff07d29f392
 0300000000000000
 3c4c000100000580
-7c0802a638428a1c
+7c0802a638428a3c
 f821ffb1480006e9
 7c7f1b78eb630000
 7cbd2b787c9c2378
@@ -907,7 +903,7 @@ f821ffb1480006e9
 4bffffb8f93f0000
 0100000000000000
 3c4c000100000580
-7c0802a63842899c
+7c0802a6384289bc
 f821ffa148000661
 7c9b23787c7d1b78
 388000007ca32b78
@@ -938,7 +934,7 @@ e95d00009b270000
 f95d0000394a0001
 000000004bffffa8
 0000078001000000
-384288a03c4c0001
+384288c03c4c0001
 480005397c0802a6
 7c741b79f821fed1
 38600000f8610060
@@ -947,7 +943,7 @@ f95d0000394a0001
 3ac4ffff3e42ffff
 f92100703b410020
 3ae0000060000000
-3a527fe039228028
+3a527fc039228008
 f92100783ba10060
 ebc1006089250000
 419e00102fa90000
diff --git a/litedram/generated/sim/litedram_core.v b/litedram/generated/sim/litedram_core.v
index f3f21e3..1e93917 100644
--- a/litedram/generated/sim/litedram_core.v
+++ b/litedram/generated/sim/litedram_core.v
@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-02 11:27:39
+// Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-05 11:21:54
 //--------------------------------------------------------------------------------
 module litedram_core(
 	input wire clk,
@@ -33,8 +33,8 @@ module litedram_core(
 
 reg [13:0] litedramcore_adr = 14'd0;
 reg litedramcore_we = 1'd0;
-wire [7:0] litedramcore_dat_w;
-wire [7:0] litedramcore_dat_r;
+wire [31:0] litedramcore_dat_w;
+wire [31:0] litedramcore_dat_r;
 wire [29:0] litedramcore_wishbone_adr;
 wire [31:0] litedramcore_wishbone_dat_w;
 wire [31:0] litedramcore_wishbone_dat_r;
@@ -1638,8 +1638,8 @@ reg new_master_rdata_valid8 = 1'd0;
 reg new_master_rdata_valid9 = 1'd0;
 wire [13:0] interface0_bank_bus_adr;
 wire interface0_bank_bus_we;
-wire [7:0] interface0_bank_bus_dat_w;
-reg [7:0] interface0_bank_bus_dat_r = 8'd0;
+wire [31:0] interface0_bank_bus_dat_w;
+reg [31:0] interface0_bank_bus_dat_r = 32'd0;
 wire csrbank0_init_done0_re;
 wire csrbank0_init_done0_r;
 wire csrbank0_init_done0_we;
@@ -1651,8 +1651,8 @@ wire csrbank0_init_error0_w;
 wire csrbank0_sel;
 wire [13:0] interface1_bank_bus_adr;
 wire interface1_bank_bus_we;
-wire [7:0] interface1_bank_bus_dat_w;
-reg [7:0] interface1_bank_bus_dat_r = 8'd0;
+wire [31:0] interface1_bank_bus_dat_w;
+reg [31:0] interface1_bank_bus_dat_r = 32'd0;
 wire csrbank1_dfii_control0_re;
 wire [3:0] csrbank1_dfii_control0_r;
 wire csrbank1_dfii_control0_we;
@@ -1661,199 +1661,87 @@ wire csrbank1_dfii_pi0_command0_re;
 wire [5:0] csrbank1_dfii_pi0_command0_r;
 wire csrbank1_dfii_pi0_command0_we;
 wire [5:0] csrbank1_dfii_pi0_command0_w;
-wire csrbank1_dfii_pi0_address1_re;
-wire [5:0] csrbank1_dfii_pi0_address1_r;
-wire csrbank1_dfii_pi0_address1_we;
-wire [5:0] csrbank1_dfii_pi0_address1_w;
 wire csrbank1_dfii_pi0_address0_re;
-wire [7:0] csrbank1_dfii_pi0_address0_r;
+wire [13:0] csrbank1_dfii_pi0_address0_r;
 wire csrbank1_dfii_pi0_address0_we;
-wire [7:0] csrbank1_dfii_pi0_address0_w;
+wire [13:0] csrbank1_dfii_pi0_address0_w;
 wire csrbank1_dfii_pi0_baddress0_re;
 wire [2:0] csrbank1_dfii_pi0_baddress0_r;
 wire csrbank1_dfii_pi0_baddress0_we;
 wire [2:0] csrbank1_dfii_pi0_baddress0_w;
-wire csrbank1_dfii_pi0_wrdata3_re;
-wire [7:0] csrbank1_dfii_pi0_wrdata3_r;
-wire csrbank1_dfii_pi0_wrdata3_we;
-wire [7:0] csrbank1_dfii_pi0_wrdata3_w;
-wire csrbank1_dfii_pi0_wrdata2_re;
-wire [7:0] csrbank1_dfii_pi0_wrdata2_r;
-wire csrbank1_dfii_pi0_wrdata2_we;
-wire [7:0] csrbank1_dfii_pi0_wrdata2_w;
-wire csrbank1_dfii_pi0_wrdata1_re;
-wire [7:0] csrbank1_dfii_pi0_wrdata1_r;
-wire csrbank1_dfii_pi0_wrdata1_we;
-wire [7:0] csrbank1_dfii_pi0_wrdata1_w;
 wire csrbank1_dfii_pi0_wrdata0_re;
-wire [7:0] csrbank1_dfii_pi0_wrdata0_r;
+wire [31:0] csrbank1_dfii_pi0_wrdata0_r;
 wire csrbank1_dfii_pi0_wrdata0_we;
-wire [7:0] csrbank1_dfii_pi0_wrdata0_w;
-wire csrbank1_dfii_pi0_rddata3_re;
-wire [7:0] csrbank1_dfii_pi0_rddata3_r;
-wire csrbank1_dfii_pi0_rddata3_we;
-wire [7:0] csrbank1_dfii_pi0_rddata3_w;
-wire csrbank1_dfii_pi0_rddata2_re;
-wire [7:0] csrbank1_dfii_pi0_rddata2_r;
-wire csrbank1_dfii_pi0_rddata2_we;
-wire [7:0] csrbank1_dfii_pi0_rddata2_w;
-wire csrbank1_dfii_pi0_rddata1_re;
-wire [7:0] csrbank1_dfii_pi0_rddata1_r;
-wire csrbank1_dfii_pi0_rddata1_we;
-wire [7:0] csrbank1_dfii_pi0_rddata1_w;
-wire csrbank1_dfii_pi0_rddata0_re;
-wire [7:0] csrbank1_dfii_pi0_rddata0_r;
-wire csrbank1_dfii_pi0_rddata0_we;
-wire [7:0] csrbank1_dfii_pi0_rddata0_w;
+wire [31:0] csrbank1_dfii_pi0_wrdata0_w;
+wire csrbank1_dfii_pi0_rddata_re;
+wire [31:0] csrbank1_dfii_pi0_rddata_r;
+wire csrbank1_dfii_pi0_rddata_we;
+wire [31:0] csrbank1_dfii_pi0_rddata_w;
 wire csrbank1_dfii_pi1_command0_re;
 wire [5:0] csrbank1_dfii_pi1_command0_r;
 wire csrbank1_dfii_pi1_command0_we;
 wire [5:0] csrbank1_dfii_pi1_command0_w;
-wire csrbank1_dfii_pi1_address1_re;
-wire [5:0] csrbank1_dfii_pi1_address1_r;
-wire csrbank1_dfii_pi1_address1_we;
-wire [5:0] csrbank1_dfii_pi1_address1_w;
 wire csrbank1_dfii_pi1_address0_re;
-wire [7:0] csrbank1_dfii_pi1_address0_r;
+wire [13:0] csrbank1_dfii_pi1_address0_r;
 wire csrbank1_dfii_pi1_address0_we;
-wire [7:0] csrbank1_dfii_pi1_address0_w;
+wire [13:0] csrbank1_dfii_pi1_address0_w;
 wire csrbank1_dfii_pi1_baddress0_re;
 wire [2:0] csrbank1_dfii_pi1_baddress0_r;
 wire csrbank1_dfii_pi1_baddress0_we;
 wire [2:0] csrbank1_dfii_pi1_baddress0_w;
-wire csrbank1_dfii_pi1_wrdata3_re;
-wire [7:0] csrbank1_dfii_pi1_wrdata3_r;
-wire csrbank1_dfii_pi1_wrdata3_we;
-wire [7:0] csrbank1_dfii_pi1_wrdata3_w;
-wire csrbank1_dfii_pi1_wrdata2_re;
-wire [7:0] csrbank1_dfii_pi1_wrdata2_r;
-wire csrbank1_dfii_pi1_wrdata2_we;
-wire [7:0] csrbank1_dfii_pi1_wrdata2_w;
-wire csrbank1_dfii_pi1_wrdata1_re;
-wire [7:0] csrbank1_dfii_pi1_wrdata1_r;
-wire csrbank1_dfii_pi1_wrdata1_we;
-wire [7:0] csrbank1_dfii_pi1_wrdata1_w;
 wire csrbank1_dfii_pi1_wrdata0_re;
-wire [7:0] csrbank1_dfii_pi1_wrdata0_r;
+wire [31:0] csrbank1_dfii_pi1_wrdata0_r;
 wire csrbank1_dfii_pi1_wrdata0_we;
-wire [7:0] csrbank1_dfii_pi1_wrdata0_w;
-wire csrbank1_dfii_pi1_rddata3_re;
-wire [7:0] csrbank1_dfii_pi1_rddata3_r;
-wire csrbank1_dfii_pi1_rddata3_we;
-wire [7:0] csrbank1_dfii_pi1_rddata3_w;
-wire csrbank1_dfii_pi1_rddata2_re;
-wire [7:0] csrbank1_dfii_pi1_rddata2_r;
-wire csrbank1_dfii_pi1_rddata2_we;
-wire [7:0] csrbank1_dfii_pi1_rddata2_w;
-wire csrbank1_dfii_pi1_rddata1_re;
-wire [7:0] csrbank1_dfii_pi1_rddata1_r;
-wire csrbank1_dfii_pi1_rddata1_we;
-wire [7:0] csrbank1_dfii_pi1_rddata1_w;
-wire csrbank1_dfii_pi1_rddata0_re;
-wire [7:0] csrbank1_dfii_pi1_rddata0_r;
-wire csrbank1_dfii_pi1_rddata0_we;
-wire [7:0] csrbank1_dfii_pi1_rddata0_w;
+wire [31:0] csrbank1_dfii_pi1_wrdata0_w;
+wire csrbank1_dfii_pi1_rddata_re;
+wire [31:0] csrbank1_dfii_pi1_rddata_r;
+wire csrbank1_dfii_pi1_rddata_we;
+wire [31:0] csrbank1_dfii_pi1_rddata_w;
 wire csrbank1_dfii_pi2_command0_re;
 wire [5:0] csrbank1_dfii_pi2_command0_r;
 wire csrbank1_dfii_pi2_command0_we;
 wire [5:0] csrbank1_dfii_pi2_command0_w;
-wire csrbank1_dfii_pi2_address1_re;
-wire [5:0] csrbank1_dfii_pi2_address1_r;
-wire csrbank1_dfii_pi2_address1_we;
-wire [5:0] csrbank1_dfii_pi2_address1_w;
 wire csrbank1_dfii_pi2_address0_re;
-wire [7:0] csrbank1_dfii_pi2_address0_r;
+wire [13:0] csrbank1_dfii_pi2_address0_r;
 wire csrbank1_dfii_pi2_address0_we;
-wire [7:0] csrbank1_dfii_pi2_address0_w;
+wire [13:0] csrbank1_dfii_pi2_address0_w;
 wire csrbank1_dfii_pi2_baddress0_re;
 wire [2:0] csrbank1_dfii_pi2_baddress0_r;
 wire csrbank1_dfii_pi2_baddress0_we;
 wire [2:0] csrbank1_dfii_pi2_baddress0_w;
-wire csrbank1_dfii_pi2_wrdata3_re;
-wire [7:0] csrbank1_dfii_pi2_wrdata3_r;
-wire csrbank1_dfii_pi2_wrdata3_we;
-wire [7:0] csrbank1_dfii_pi2_wrdata3_w;
-wire csrbank1_dfii_pi2_wrdata2_re;
-wire [7:0] csrbank1_dfii_pi2_wrdata2_r;
-wire csrbank1_dfii_pi2_wrdata2_we;
-wire [7:0] csrbank1_dfii_pi2_wrdata2_w;
-wire csrbank1_dfii_pi2_wrdata1_re;
-wire [7:0] csrbank1_dfii_pi2_wrdata1_r;
-wire csrbank1_dfii_pi2_wrdata1_we;
-wire [7:0] csrbank1_dfii_pi2_wrdata1_w;
 wire csrbank1_dfii_pi2_wrdata0_re;
-wire [7:0] csrbank1_dfii_pi2_wrdata0_r;
+wire [31:0] csrbank1_dfii_pi2_wrdata0_r;
 wire csrbank1_dfii_pi2_wrdata0_we;
-wire [7:0] csrbank1_dfii_pi2_wrdata0_w;
-wire csrbank1_dfii_pi2_rddata3_re;
-wire [7:0] csrbank1_dfii_pi2_rddata3_r;
-wire csrbank1_dfii_pi2_rddata3_we;
-wire [7:0] csrbank1_dfii_pi2_rddata3_w;
-wire csrbank1_dfii_pi2_rddata2_re;
-wire [7:0] csrbank1_dfii_pi2_rddata2_r;
-wire csrbank1_dfii_pi2_rddata2_we;
-wire [7:0] csrbank1_dfii_pi2_rddata2_w;
-wire csrbank1_dfii_pi2_rddata1_re;
-wire [7:0] csrbank1_dfii_pi2_rddata1_r;
-wire csrbank1_dfii_pi2_rddata1_we;
-wire [7:0] csrbank1_dfii_pi2_rddata1_w;
-wire csrbank1_dfii_pi2_rddata0_re;
-wire [7:0] csrbank1_dfii_pi2_rddata0_r;
-wire csrbank1_dfii_pi2_rddata0_we;
-wire [7:0] csrbank1_dfii_pi2_rddata0_w;
+wire [31:0] csrbank1_dfii_pi2_wrdata0_w;
+wire csrbank1_dfii_pi2_rddata_re;
+wire [31:0] csrbank1_dfii_pi2_rddata_r;
+wire csrbank1_dfii_pi2_rddata_we;
+wire [31:0] csrbank1_dfii_pi2_rddata_w;
 wire csrbank1_dfii_pi3_command0_re;
 wire [5:0] csrbank1_dfii_pi3_command0_r;
 wire csrbank1_dfii_pi3_command0_we;
 wire [5:0] csrbank1_dfii_pi3_command0_w;
-wire csrbank1_dfii_pi3_address1_re;
-wire [5:0] csrbank1_dfii_pi3_address1_r;
-wire csrbank1_dfii_pi3_address1_we;
-wire [5:0] csrbank1_dfii_pi3_address1_w;
 wire csrbank1_dfii_pi3_address0_re;
-wire [7:0] csrbank1_dfii_pi3_address0_r;
+wire [13:0] csrbank1_dfii_pi3_address0_r;
 wire csrbank1_dfii_pi3_address0_we;
-wire [7:0] csrbank1_dfii_pi3_address0_w;
+wire [13:0] csrbank1_dfii_pi3_address0_w;
 wire csrbank1_dfii_pi3_baddress0_re;
 wire [2:0] csrbank1_dfii_pi3_baddress0_r;
 wire csrbank1_dfii_pi3_baddress0_we;
 wire [2:0] csrbank1_dfii_pi3_baddress0_w;
-wire csrbank1_dfii_pi3_wrdata3_re;
-wire [7:0] csrbank1_dfii_pi3_wrdata3_r;
-wire csrbank1_dfii_pi3_wrdata3_we;
-wire [7:0] csrbank1_dfii_pi3_wrdata3_w;
-wire csrbank1_dfii_pi3_wrdata2_re;
-wire [7:0] csrbank1_dfii_pi3_wrdata2_r;
-wire csrbank1_dfii_pi3_wrdata2_we;
-wire [7:0] csrbank1_dfii_pi3_wrdata2_w;
-wire csrbank1_dfii_pi3_wrdata1_re;
-wire [7:0] csrbank1_dfii_pi3_wrdata1_r;
-wire csrbank1_dfii_pi3_wrdata1_we;
-wire [7:0] csrbank1_dfii_pi3_wrdata1_w;
 wire csrbank1_dfii_pi3_wrdata0_re;
-wire [7:0] csrbank1_dfii_pi3_wrdata0_r;
+wire [31:0] csrbank1_dfii_pi3_wrdata0_r;
 wire csrbank1_dfii_pi3_wrdata0_we;
-wire [7:0] csrbank1_dfii_pi3_wrdata0_w;
-wire csrbank1_dfii_pi3_rddata3_re;
-wire [7:0] csrbank1_dfii_pi3_rddata3_r;
-wire csrbank1_dfii_pi3_rddata3_we;
-wire [7:0] csrbank1_dfii_pi3_rddata3_w;
-wire csrbank1_dfii_pi3_rddata2_re;
-wire [7:0] csrbank1_dfii_pi3_rddata2_r;
-wire csrbank1_dfii_pi3_rddata2_we;
-wire [7:0] csrbank1_dfii_pi3_rddata2_w;
-wire csrbank1_dfii_pi3_rddata1_re;
-wire [7:0] csrbank1_dfii_pi3_rddata1_r;
-wire csrbank1_dfii_pi3_rddata1_we;
-wire [7:0] csrbank1_dfii_pi3_rddata1_w;
-wire csrbank1_dfii_pi3_rddata0_re;
-wire [7:0] csrbank1_dfii_pi3_rddata0_r;
-wire csrbank1_dfii_pi3_rddata0_we;
-wire [7:0] csrbank1_dfii_pi3_rddata0_w;
+wire [31:0] csrbank1_dfii_pi3_wrdata0_w;
+wire csrbank1_dfii_pi3_rddata_re;
+wire [31:0] csrbank1_dfii_pi3_rddata_r;
+wire csrbank1_dfii_pi3_rddata_we;
+wire [31:0] csrbank1_dfii_pi3_rddata_w;
 wire csrbank1_sel;
 wire [13:0] adr;
 wire we;
-wire [7:0] dat_w;
-wire [7:0] dat_r;
+wire [31:0] dat_w;
+wire [31:0] dat_r;
 wire [24:0] slice_proxy0;
 wire [24:0] slice_proxy1;
 wire [24:0] slice_proxy2;
@@ -9892,217 +9780,105 @@ assign csrbank0_init_done0_w = init_done_storage;
 assign csrbank0_init_error0_w = init_error_storage;
 assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
 assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0];
-assign csrbank1_dfii_control0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 1'd0));
-assign csrbank1_dfii_control0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 1'd0));
+assign csrbank1_dfii_control0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 1'd0));
+assign csrbank1_dfii_control0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 1'd0));
 assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[5:0];
-assign csrbank1_dfii_pi0_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 1'd1));
-assign csrbank1_dfii_pi0_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 1'd1));
+assign csrbank1_dfii_pi0_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 1'd1));
+assign csrbank1_dfii_pi0_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 1'd1));
 assign litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector0_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 2'd2));
-assign litedramcore_phaseinjector0_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 2'd2));
-assign csrbank1_dfii_pi0_address1_r = interface1_bank_bus_dat_w[5:0];
-assign csrbank1_dfii_pi0_address1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 2'd3));
-assign csrbank1_dfii_pi0_address1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 2'd3));
-assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi0_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 3'd4));
-assign csrbank1_dfii_pi0_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 3'd4));
+assign litedramcore_phaseinjector0_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 2'd2));
+assign litedramcore_phaseinjector0_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 2'd2));
+assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[13:0];
+assign csrbank1_dfii_pi0_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 2'd3));
+assign csrbank1_dfii_pi0_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 2'd3));
 assign csrbank1_dfii_pi0_baddress0_r = interface1_bank_bus_dat_w[2:0];
-assign csrbank1_dfii_pi0_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 3'd5));
-assign csrbank1_dfii_pi0_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 3'd5));
-assign csrbank1_dfii_pi0_wrdata3_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi0_wrdata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 3'd6));
-assign csrbank1_dfii_pi0_wrdata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 3'd6));
-assign csrbank1_dfii_pi0_wrdata2_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi0_wrdata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 3'd7));
-assign csrbank1_dfii_pi0_wrdata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 3'd7));
-assign csrbank1_dfii_pi0_wrdata1_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi0_wrdata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd8));
-assign csrbank1_dfii_pi0_wrdata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd8));
-assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi0_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd9));
-assign csrbank1_dfii_pi0_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd9));
-assign csrbank1_dfii_pi0_rddata3_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi0_rddata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd10));
-assign csrbank1_dfii_pi0_rddata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd10));
-assign csrbank1_dfii_pi0_rddata2_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi0_rddata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd11));
-assign csrbank1_dfii_pi0_rddata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd11));
-assign csrbank1_dfii_pi0_rddata1_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi0_rddata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd12));
-assign csrbank1_dfii_pi0_rddata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd12));
-assign csrbank1_dfii_pi0_rddata0_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi0_rddata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd13));
-assign csrbank1_dfii_pi0_rddata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd13));
+assign csrbank1_dfii_pi0_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd4));
+assign csrbank1_dfii_pi0_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd4));
+assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[31:0];
+assign csrbank1_dfii_pi0_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd5));
+assign csrbank1_dfii_pi0_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd5));
+assign csrbank1_dfii_pi0_rddata_r = interface1_bank_bus_dat_w[31:0];
+assign csrbank1_dfii_pi0_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd6));
+assign csrbank1_dfii_pi0_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd6));
 assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[5:0];
-assign csrbank1_dfii_pi1_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd14));
-assign csrbank1_dfii_pi1_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd14));
+assign csrbank1_dfii_pi1_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd7));
+assign csrbank1_dfii_pi1_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd7));
 assign litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector1_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd15));
-assign litedramcore_phaseinjector1_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd15));
-assign csrbank1_dfii_pi1_address1_r = interface1_bank_bus_dat_w[5:0];
-assign csrbank1_dfii_pi1_address1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd16));
-assign csrbank1_dfii_pi1_address1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd16));
-assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi1_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd17));
-assign csrbank1_dfii_pi1_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd17));
+assign litedramcore_phaseinjector1_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd8));
+assign litedramcore_phaseinjector1_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd8));
+assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[13:0];
+assign csrbank1_dfii_pi1_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd9));
+assign csrbank1_dfii_pi1_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd9));
 assign csrbank1_dfii_pi1_baddress0_r = interface1_bank_bus_dat_w[2:0];
-assign csrbank1_dfii_pi1_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd18));
-assign csrbank1_dfii_pi1_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd18));
-assign csrbank1_dfii_pi1_wrdata3_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi1_wrdata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd19));
-assign csrbank1_dfii_pi1_wrdata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd19));
-assign csrbank1_dfii_pi1_wrdata2_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi1_wrdata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd20));
-assign csrbank1_dfii_pi1_wrdata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd20));
-assign csrbank1_dfii_pi1_wrdata1_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi1_wrdata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd21));
-assign csrbank1_dfii_pi1_wrdata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd21));
-assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi1_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd22));
-assign csrbank1_dfii_pi1_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd22));
-assign csrbank1_dfii_pi1_rddata3_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi1_rddata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd23));
-assign csrbank1_dfii_pi1_rddata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd23));
-assign csrbank1_dfii_pi1_rddata2_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi1_rddata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd24));
-assign csrbank1_dfii_pi1_rddata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd24));
-assign csrbank1_dfii_pi1_rddata1_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi1_rddata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd25));
-assign csrbank1_dfii_pi1_rddata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd25));
-assign csrbank1_dfii_pi1_rddata0_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi1_rddata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd26));
-assign csrbank1_dfii_pi1_rddata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd26));
+assign csrbank1_dfii_pi1_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd10));
+assign csrbank1_dfii_pi1_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd10));
+assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[31:0];
+assign csrbank1_dfii_pi1_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd11));
+assign csrbank1_dfii_pi1_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd11));
+assign csrbank1_dfii_pi1_rddata_r = interface1_bank_bus_dat_w[31:0];
+assign csrbank1_dfii_pi1_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd12));
+assign csrbank1_dfii_pi1_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd12));
 assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[5:0];
-assign csrbank1_dfii_pi2_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd27));
-assign csrbank1_dfii_pi2_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd27));
+assign csrbank1_dfii_pi2_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd13));
+assign csrbank1_dfii_pi2_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd13));
 assign litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector2_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd28));
-assign litedramcore_phaseinjector2_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd28));
-assign csrbank1_dfii_pi2_address1_r = interface1_bank_bus_dat_w[5:0];
-assign csrbank1_dfii_pi2_address1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd29));
-assign csrbank1_dfii_pi2_address1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd29));
-assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi2_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd30));
-assign csrbank1_dfii_pi2_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd30));
+assign litedramcore_phaseinjector2_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd14));
+assign litedramcore_phaseinjector2_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd14));
+assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[13:0];
+assign csrbank1_dfii_pi2_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd15));
+assign csrbank1_dfii_pi2_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd15));
 assign csrbank1_dfii_pi2_baddress0_r = interface1_bank_bus_dat_w[2:0];
-assign csrbank1_dfii_pi2_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd31));
-assign csrbank1_dfii_pi2_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd31));
-assign csrbank1_dfii_pi2_wrdata3_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi2_wrdata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd32));
-assign csrbank1_dfii_pi2_wrdata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd32));
-assign csrbank1_dfii_pi2_wrdata2_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi2_wrdata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd33));
-assign csrbank1_dfii_pi2_wrdata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd33));
-assign csrbank1_dfii_pi2_wrdata1_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi2_wrdata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd34));
-assign csrbank1_dfii_pi2_wrdata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd34));
-assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi2_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd35));
-assign csrbank1_dfii_pi2_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd35));
-assign csrbank1_dfii_pi2_rddata3_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi2_rddata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd36));
-assign csrbank1_dfii_pi2_rddata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd36));
-assign csrbank1_dfii_pi2_rddata2_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi2_rddata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd37));
-assign csrbank1_dfii_pi2_rddata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd37));
-assign csrbank1_dfii_pi2_rddata1_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi2_rddata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd38));
-assign csrbank1_dfii_pi2_rddata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd38));
-assign csrbank1_dfii_pi2_rddata0_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi2_rddata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd39));
-assign csrbank1_dfii_pi2_rddata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd39));
+assign csrbank1_dfii_pi2_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd16));
+assign csrbank1_dfii_pi2_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd16));
+assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[31:0];
+assign csrbank1_dfii_pi2_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd17));
+assign csrbank1_dfii_pi2_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd17));
+assign csrbank1_dfii_pi2_rddata_r = interface1_bank_bus_dat_w[31:0];
+assign csrbank1_dfii_pi2_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd18));
+assign csrbank1_dfii_pi2_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd18));
 assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[5:0];
-assign csrbank1_dfii_pi3_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd40));
-assign csrbank1_dfii_pi3_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd40));
+assign csrbank1_dfii_pi3_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd19));
+assign csrbank1_dfii_pi3_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd19));
 assign litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector3_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd41));
-assign litedramcore_phaseinjector3_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd41));
-assign csrbank1_dfii_pi3_address1_r = interface1_bank_bus_dat_w[5:0];
-assign csrbank1_dfii_pi3_address1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd42));
-assign csrbank1_dfii_pi3_address1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd42));
-assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi3_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd43));
-assign csrbank1_dfii_pi3_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd43));
+assign litedramcore_phaseinjector3_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd20));
+assign litedramcore_phaseinjector3_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd20));
+assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[13:0];
+assign csrbank1_dfii_pi3_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd21));
+assign csrbank1_dfii_pi3_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd21));
 assign csrbank1_dfii_pi3_baddress0_r = interface1_bank_bus_dat_w[2:0];
-assign csrbank1_dfii_pi3_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd44));
-assign csrbank1_dfii_pi3_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd44));
-assign csrbank1_dfii_pi3_wrdata3_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi3_wrdata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd45));
-assign csrbank1_dfii_pi3_wrdata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd45));
-assign csrbank1_dfii_pi3_wrdata2_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi3_wrdata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd46));
-assign csrbank1_dfii_pi3_wrdata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd46));
-assign csrbank1_dfii_pi3_wrdata1_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi3_wrdata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd47));
-assign csrbank1_dfii_pi3_wrdata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd47));
-assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi3_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd48));
-assign csrbank1_dfii_pi3_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd48));
-assign csrbank1_dfii_pi3_rddata3_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi3_rddata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd49));
-assign csrbank1_dfii_pi3_rddata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd49));
-assign csrbank1_dfii_pi3_rddata2_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi3_rddata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd50));
-assign csrbank1_dfii_pi3_rddata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd50));
-assign csrbank1_dfii_pi3_rddata1_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi3_rddata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd51));
-assign csrbank1_dfii_pi3_rddata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd51));
-assign csrbank1_dfii_pi3_rddata0_r = interface1_bank_bus_dat_w[7:0];
-assign csrbank1_dfii_pi3_rddata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd52));
-assign csrbank1_dfii_pi3_rddata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd52));
+assign csrbank1_dfii_pi3_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd22));
+assign csrbank1_dfii_pi3_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd22));
+assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[31:0];
+assign csrbank1_dfii_pi3_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd23));
+assign csrbank1_dfii_pi3_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd23));
+assign csrbank1_dfii_pi3_rddata_r = interface1_bank_bus_dat_w[31:0];
+assign csrbank1_dfii_pi3_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd24));
+assign csrbank1_dfii_pi3_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd24));
 assign csrbank1_dfii_control0_w = litedramcore_storage[3:0];
 assign csrbank1_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
-assign csrbank1_dfii_pi0_address1_w = litedramcore_phaseinjector0_address_storage[13:8];
-assign csrbank1_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[7:0];
+assign csrbank1_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0];
 assign csrbank1_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
-assign csrbank1_dfii_pi0_wrdata3_w = litedramcore_phaseinjector0_wrdata_storage[31:24];
-assign csrbank1_dfii_pi0_wrdata2_w = litedramcore_phaseinjector0_wrdata_storage[23:16];
-assign csrbank1_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[15:8];
-assign csrbank1_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[7:0];
-assign csrbank1_dfii_pi0_rddata3_w = litedramcore_phaseinjector0_status[31:24];
-assign csrbank1_dfii_pi0_rddata2_w = litedramcore_phaseinjector0_status[23:16];
-assign csrbank1_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_status[15:8];
-assign csrbank1_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_status[7:0];
-assign litedramcore_phaseinjector0_we = csrbank1_dfii_pi0_rddata0_we;
+assign csrbank1_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
+assign csrbank1_dfii_pi0_rddata_w = litedramcore_phaseinjector0_status[31:0];
+assign litedramcore_phaseinjector0_we = csrbank1_dfii_pi0_rddata_we;
 assign csrbank1_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
-assign csrbank1_dfii_pi1_address1_w = litedramcore_phaseinjector1_address_storage[13:8];
-assign csrbank1_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[7:0];
+assign csrbank1_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[13:0];
 assign csrbank1_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
-assign csrbank1_dfii_pi1_wrdata3_w = litedramcore_phaseinjector1_wrdata_storage[31:24];
-assign csrbank1_dfii_pi1_wrdata2_w = litedramcore_phaseinjector1_wrdata_storage[23:16];
-assign csrbank1_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[15:8];
-assign csrbank1_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[7:0];
-assign csrbank1_dfii_pi1_rddata3_w = litedramcore_phaseinjector1_status[31:24];
-assign csrbank1_dfii_pi1_rddata2_w = litedramcore_phaseinjector1_status[23:16];
-assign csrbank1_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_status[15:8];
-assign csrbank1_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_status[7:0];
-assign litedramcore_phaseinjector1_we = csrbank1_dfii_pi1_rddata0_we;
+assign csrbank1_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
+assign csrbank1_dfii_pi1_rddata_w = litedramcore_phaseinjector1_status[31:0];
+assign litedramcore_phaseinjector1_we = csrbank1_dfii_pi1_rddata_we;
 assign csrbank1_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
-assign csrbank1_dfii_pi2_address1_w = litedramcore_phaseinjector2_address_storage[13:8];
-assign csrbank1_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[7:0];
+assign csrbank1_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[13:0];
 assign csrbank1_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
-assign csrbank1_dfii_pi2_wrdata3_w = litedramcore_phaseinjector2_wrdata_storage[31:24];
-assign csrbank1_dfii_pi2_wrdata2_w = litedramcore_phaseinjector2_wrdata_storage[23:16];
-assign csrbank1_dfii_pi2_wrdata1_w = litedramcore_phaseinjector2_wrdata_storage[15:8];
-assign csrbank1_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[7:0];
-assign csrbank1_dfii_pi2_rddata3_w = litedramcore_phaseinjector2_status[31:24];
-assign csrbank1_dfii_pi2_rddata2_w = litedramcore_phaseinjector2_status[23:16];
-assign csrbank1_dfii_pi2_rddata1_w = litedramcore_phaseinjector2_status[15:8];
-assign csrbank1_dfii_pi2_rddata0_w = litedramcore_phaseinjector2_status[7:0];
-assign litedramcore_phaseinjector2_we = csrbank1_dfii_pi2_rddata0_we;
+assign csrbank1_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0];
+assign csrbank1_dfii_pi2_rddata_w = litedramcore_phaseinjector2_status[31:0];
+assign litedramcore_phaseinjector2_we = csrbank1_dfii_pi2_rddata_we;
 assign csrbank1_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
-assign csrbank1_dfii_pi3_address1_w = litedramcore_phaseinjector3_address_storage[13:8];
-assign csrbank1_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[7:0];
+assign csrbank1_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[13:0];
 assign csrbank1_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
-assign csrbank1_dfii_pi3_wrdata3_w = litedramcore_phaseinjector3_wrdata_storage[31:24];
-assign csrbank1_dfii_pi3_wrdata2_w = litedramcore_phaseinjector3_wrdata_storage[23:16];
-assign csrbank1_dfii_pi3_wrdata1_w = litedramcore_phaseinjector3_wrdata_storage[15:8];
-assign csrbank1_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[7:0];
-assign csrbank1_dfii_pi3_rddata3_w = litedramcore_phaseinjector3_status[31:24];
-assign csrbank1_dfii_pi3_rddata2_w = litedramcore_phaseinjector3_status[23:16];
-assign csrbank1_dfii_pi3_rddata1_w = litedramcore_phaseinjector3_status[15:8];
-assign csrbank1_dfii_pi3_rddata0_w = litedramcore_phaseinjector3_status[7:0];
-assign litedramcore_phaseinjector3_we = csrbank1_dfii_pi3_rddata0_we;
+assign csrbank1_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0];
+assign csrbank1_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0];
+assign litedramcore_phaseinjector3_we = csrbank1_dfii_pi3_rddata_we;
 assign adr = litedramcore_adr;
 assign we = litedramcore_we;
 assign dat_w = litedramcore_dat_w;
@@ -12768,7 +12544,7 @@ always @(posedge sys_clk) begin
 	init_error_re <= csrbank0_init_error0_re;
 	interface1_bank_bus_dat_r <= 1'd0;
 	if (csrbank1_sel) begin
-		case (interface1_bank_bus_adr[5:0])
+		case (interface1_bank_bus_adr[4:0])
 			1'd0: begin
 				interface1_bank_bus_dat_r <= csrbank1_dfii_control0_w;
 			end
@@ -12779,154 +12555,70 @@ always @(posedge sys_clk) begin
 				interface1_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
 			end
 			2'd3: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address1_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w;
 			end
 			3'd4: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w;
 			end
 			3'd5: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w;
 			end
 			3'd6: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata3_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata_w;
 			end
 			3'd7: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata2_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w;
 			end
 			4'd8: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata1_w;
+				interface1_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
 			end
 			4'd9: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w;
 			end
 			4'd10: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata3_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w;
 			end
 			4'd11: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata2_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w;
 			end
 			4'd12: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata1_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata_w;
 			end
 			4'd13: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata0_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w;
 			end
 			4'd14: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w;
+				interface1_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
 			end
 			4'd15: begin
-				interface1_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w;
 			end
 			5'd16: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address1_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w;
 			end
 			5'd17: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w;
 			end
 			5'd18: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w;
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata_w;
 			end
 			5'd19: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata3_w;
-			end
-			5'd20: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata2_w;
-			end
-			5'd21: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata1_w;
-			end
-			5'd22: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w;
-			end
-			5'd23: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata3_w;
-			end
-			5'd24: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata2_w;
-			end
-			5'd25: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata1_w;
-			end
-			5'd26: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata0_w;
-			end
-			5'd27: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w;
-			end
-			5'd28: begin
-				interface1_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
-			end
-			5'd29: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address1_w;
-			end
-			5'd30: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w;
-			end
-			5'd31: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w;
-			end
-			6'd32: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata3_w;
-			end
-			6'd33: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata2_w;
-			end
-			6'd34: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata1_w;
-			end
-			6'd35: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w;
-			end
-			6'd36: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata3_w;
-			end
-			6'd37: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata2_w;
-			end
-			6'd38: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata1_w;
-			end
-			6'd39: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata0_w;
-			end
-			6'd40: begin
 				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_command0_w;
 			end
-			6'd41: begin
+			5'd20: begin
 				interface1_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
 			end
-			6'd42: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address1_w;
-			end
-			6'd43: begin
+			5'd21: begin
 				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address0_w;
 			end
-			6'd44: begin
+			5'd22: begin
 				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_baddress0_w;
 			end
-			6'd45: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata3_w;
-			end
-			6'd46: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata2_w;
-			end
-			6'd47: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata1_w;
-			end
-			6'd48: begin
+			5'd23: begin
 				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata0_w;
 			end
-			6'd49: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata3_w;
-			end
-			6'd50: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata2_w;
-			end
-			6'd51: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata1_w;
-			end
-			6'd52: begin
-				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata0_w;
+			5'd24: begin
+				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata_w;
 			end
 		endcase
 	end
@@ -12938,112 +12630,64 @@ always @(posedge sys_clk) begin
 		litedramcore_phaseinjector0_command_storage[5:0] <= csrbank1_dfii_pi0_command0_r;
 	end
 	litedramcore_phaseinjector0_command_re <= csrbank1_dfii_pi0_command0_re;
-	if (csrbank1_dfii_pi0_address1_re) begin
-		litedramcore_phaseinjector0_address_storage[13:8] <= csrbank1_dfii_pi0_address1_r;
-	end
 	if (csrbank1_dfii_pi0_address0_re) begin
-		litedramcore_phaseinjector0_address_storage[7:0] <= csrbank1_dfii_pi0_address0_r;
+		litedramcore_phaseinjector0_address_storage[13:0] <= csrbank1_dfii_pi0_address0_r;
 	end
 	litedramcore_phaseinjector0_address_re <= csrbank1_dfii_pi0_address0_re;
 	if (csrbank1_dfii_pi0_baddress0_re) begin
 		litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank1_dfii_pi0_baddress0_r;
 	end
 	litedramcore_phaseinjector0_baddress_re <= csrbank1_dfii_pi0_baddress0_re;
-	if (csrbank1_dfii_pi0_wrdata3_re) begin
-		litedramcore_phaseinjector0_wrdata_storage[31:24] <= csrbank1_dfii_pi0_wrdata3_r;
-	end
-	if (csrbank1_dfii_pi0_wrdata2_re) begin
-		litedramcore_phaseinjector0_wrdata_storage[23:16] <= csrbank1_dfii_pi0_wrdata2_r;
-	end
-	if (csrbank1_dfii_pi0_wrdata1_re) begin
-		litedramcore_phaseinjector0_wrdata_storage[15:8] <= csrbank1_dfii_pi0_wrdata1_r;
-	end
 	if (csrbank1_dfii_pi0_wrdata0_re) begin
-		litedramcore_phaseinjector0_wrdata_storage[7:0] <= csrbank1_dfii_pi0_wrdata0_r;
+		litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank1_dfii_pi0_wrdata0_r;
 	end
 	litedramcore_phaseinjector0_wrdata_re <= csrbank1_dfii_pi0_wrdata0_re;
 	if (csrbank1_dfii_pi1_command0_re) begin
 		litedramcore_phaseinjector1_command_storage[5:0] <= csrbank1_dfii_pi1_command0_r;
 	end
 	litedramcore_phaseinjector1_command_re <= csrbank1_dfii_pi1_command0_re;
-	if (csrbank1_dfii_pi1_address1_re) begin
-		litedramcore_phaseinjector1_address_storage[13:8] <= csrbank1_dfii_pi1_address1_r;
-	end
 	if (csrbank1_dfii_pi1_address0_re) begin
-		litedramcore_phaseinjector1_address_storage[7:0] <= csrbank1_dfii_pi1_address0_r;
+		litedramcore_phaseinjector1_address_storage[13:0] <= csrbank1_dfii_pi1_address0_r;
 	end
 	litedramcore_phaseinjector1_address_re <= csrbank1_dfii_pi1_address0_re;
 	if (csrbank1_dfii_pi1_baddress0_re) begin
 		litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank1_dfii_pi1_baddress0_r;
 	end
 	litedramcore_phaseinjector1_baddress_re <= csrbank1_dfii_pi1_baddress0_re;
-	if (csrbank1_dfii_pi1_wrdata3_re) begin
-		litedramcore_phaseinjector1_wrdata_storage[31:24] <= csrbank1_dfii_pi1_wrdata3_r;
-	end
-	if (csrbank1_dfii_pi1_wrdata2_re) begin
-		litedramcore_phaseinjector1_wrdata_storage[23:16] <= csrbank1_dfii_pi1_wrdata2_r;
-	end
-	if (csrbank1_dfii_pi1_wrdata1_re) begin
-		litedramcore_phaseinjector1_wrdata_storage[15:8] <= csrbank1_dfii_pi1_wrdata1_r;
-	end
 	if (csrbank1_dfii_pi1_wrdata0_re) begin
-		litedramcore_phaseinjector1_wrdata_storage[7:0] <= csrbank1_dfii_pi1_wrdata0_r;
+		litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank1_dfii_pi1_wrdata0_r;
 	end
 	litedramcore_phaseinjector1_wrdata_re <= csrbank1_dfii_pi1_wrdata0_re;
 	if (csrbank1_dfii_pi2_command0_re) begin
 		litedramcore_phaseinjector2_command_storage[5:0] <= csrbank1_dfii_pi2_command0_r;
 	end
 	litedramcore_phaseinjector2_command_re <= csrbank1_dfii_pi2_command0_re;
-	if (csrbank1_dfii_pi2_address1_re) begin
-		litedramcore_phaseinjector2_address_storage[13:8] <= csrbank1_dfii_pi2_address1_r;
-	end
 	if (csrbank1_dfii_pi2_address0_re) begin
-		litedramcore_phaseinjector2_address_storage[7:0] <= csrbank1_dfii_pi2_address0_r;
+		litedramcore_phaseinjector2_address_storage[13:0] <= csrbank1_dfii_pi2_address0_r;
 	end
 	litedramcore_phaseinjector2_address_re <= csrbank1_dfii_pi2_address0_re;
 	if (csrbank1_dfii_pi2_baddress0_re) begin
 		litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank1_dfii_pi2_baddress0_r;
 	end
 	litedramcore_phaseinjector2_baddress_re <= csrbank1_dfii_pi2_baddress0_re;
-	if (csrbank1_dfii_pi2_wrdata3_re) begin
-		litedramcore_phaseinjector2_wrdata_storage[31:24] <= csrbank1_dfii_pi2_wrdata3_r;
-	end
-	if (csrbank1_dfii_pi2_wrdata2_re) begin
-		litedramcore_phaseinjector2_wrdata_storage[23:16] <= csrbank1_dfii_pi2_wrdata2_r;
-	end
-	if (csrbank1_dfii_pi2_wrdata1_re) begin
-		litedramcore_phaseinjector2_wrdata_storage[15:8] <= csrbank1_dfii_pi2_wrdata1_r;
-	end
 	if (csrbank1_dfii_pi2_wrdata0_re) begin
-		litedramcore_phaseinjector2_wrdata_storage[7:0] <= csrbank1_dfii_pi2_wrdata0_r;
+		litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank1_dfii_pi2_wrdata0_r;
 	end
 	litedramcore_phaseinjector2_wrdata_re <= csrbank1_dfii_pi2_wrdata0_re;
 	if (csrbank1_dfii_pi3_command0_re) begin
 		litedramcore_phaseinjector3_command_storage[5:0] <= csrbank1_dfii_pi3_command0_r;
 	end
 	litedramcore_phaseinjector3_command_re <= csrbank1_dfii_pi3_command0_re;
-	if (csrbank1_dfii_pi3_address1_re) begin
-		litedramcore_phaseinjector3_address_storage[13:8] <= csrbank1_dfii_pi3_address1_r;
-	end
 	if (csrbank1_dfii_pi3_address0_re) begin
-		litedramcore_phaseinjector3_address_storage[7:0] <= csrbank1_dfii_pi3_address0_r;
+		litedramcore_phaseinjector3_address_storage[13:0] <= csrbank1_dfii_pi3_address0_r;
 	end
 	litedramcore_phaseinjector3_address_re <= csrbank1_dfii_pi3_address0_re;
 	if (csrbank1_dfii_pi3_baddress0_re) begin
 		litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank1_dfii_pi3_baddress0_r;
 	end
 	litedramcore_phaseinjector3_baddress_re <= csrbank1_dfii_pi3_baddress0_re;
-	if (csrbank1_dfii_pi3_wrdata3_re) begin
-		litedramcore_phaseinjector3_wrdata_storage[31:24] <= csrbank1_dfii_pi3_wrdata3_r;
-	end
-	if (csrbank1_dfii_pi3_wrdata2_re) begin
-		litedramcore_phaseinjector3_wrdata_storage[23:16] <= csrbank1_dfii_pi3_wrdata2_r;
-	end
-	if (csrbank1_dfii_pi3_wrdata1_re) begin
-		litedramcore_phaseinjector3_wrdata_storage[15:8] <= csrbank1_dfii_pi3_wrdata1_r;
-	end
 	if (csrbank1_dfii_pi3_wrdata0_re) begin
-		litedramcore_phaseinjector3_wrdata_storage[7:0] <= csrbank1_dfii_pi3_wrdata0_r;
+		litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank1_dfii_pi3_wrdata0_r;
 	end
 	litedramcore_phaseinjector3_wrdata_re <= csrbank1_dfii_pi3_wrdata0_re;
 	if (sys_rst) begin