From: lkcl <lkcl@web>
Date: Sun, 13 Dec 2020 23:50:54 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1335
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=59a64a86768bc325de7c7df954696bf66bf01dc8;p=libreriscv.git

---

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 01c7b24d3..87e084e9a 100644
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -218,7 +218,7 @@ standard vector instruction with Rc=1.
 # Register Profiles
 
 Instructions are broken down by Register Profiles as listed in the following auto-generated page:
-[[opcode_regs_deduped]]
+[[opcode_regs_deduped]].  "Non-SV" indicates that the operations with this Register Profile cannot be Vectorised (dcbz, twi)
 
 ## LDST-1R-1W-imm
 TBD
@@ -249,9 +249,9 @@ non-SV
 ## 1W-CRi
 TBD
 ## 1R
-TBD
+non-SV
 ## 1R-imm
-TBD
+non-SV
 ## 1R-CRo
 TBD
 ## 1R-CRio
@@ -267,7 +267,7 @@ TBD
 ## 1R-1W-CRio
 TBD
 ## 2R
-TBD
+non-SV
 ## 2R-CRo
 TBD
 ## 2R-CRio