From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 17 Apr 2021 19:03:34 +0000 (+0100)
Subject: add LD/ST radix unit test
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=59a8fa1365c3f27aab4dbe9cbaeee416bc7a97f1;p=soc.git

add LD/ST radix unit test
---

diff --git a/src/soc/decoder/isa/test_caller_radix.py b/src/soc/decoder/isa/test_caller_radix.py
index 92f59170..40ab2b2a 100644
--- a/src/soc/decoder/isa/test_caller_radix.py
+++ b/src/soc/decoder/isa/test_caller_radix.py
@@ -12,10 +12,9 @@ from soc.decoder.orderedset import OrderedSet
 from soc.decoder.isa.all import ISA
 from soc.decoder.isa.test_caller import run_tst
 
-testmem = {
+from copy import deepcopy
 
-           0x1000: # data to be read
-           0x1337,
+testmem = {
 
            0x10000:    # PARTITION_TABLE_2 (not implemented yet)
                        # PATB_GR=1 PRTB=0x1000 PRTS=0xb
@@ -38,25 +37,41 @@ prtbl = 0x1000000
 
 class DecoderTestCase(FHDLTestCase):
 
+    def test_load(self):
+        lst = [ "lwz 3, 0(1)"
+               ]
+        with Program(lst, bigendian=False) as program:
+            initial_regs=[0] * 32
+            initial_regs[1] = 0x1000
+            initial_regs[2] = 0x1234
+
+            initial_mem = deepcopy(testmem)
+            initial_mem[0x1000] = 0x1337 # data to be read
+
+            sim = self.run_tst_program(program, initial_regs=initial_regs,
+                                                initial_mem=initial_mem)
+            self.assertEqual(sim.gpr(3), SelectableInt(0x1337, 64))
+
     def test_load_store(self):
-        lst = [#"addi 1, 0, 0x1000",
-               #"addi 2, 0, 0x1234",
-               #"stw 2, 0(1)",
+        lst = ["addi 1, 0, 0x1000",
+               "addi 2, 0, 0x1234",
+               "stw 2, 0(1)",
                "lwz 3, 0(1)"
                ]
         with Program(lst, bigendian=False) as program:
             initial_regs=[0] * 32
             initial_regs[1] = 0x1000
             initial_regs[2] = 0x1234
-            sim = self.run_tst_program(program,initial_regs=initial_regs)
-            #dump registers into file
-            #f = open("/tmp/debug.txt","w")
-            #for i in range(1,12):
-            #    l = "r"+str(i)+" = "+str(sim.gpr(i))+"\n"
-            #    f.write(l)
-            self.assertEqual(sim.gpr(3), SelectableInt(0x1337, 64))
+            initial_mem = deepcopy(testmem)
+            sim = self.run_tst_program(program, initial_regs=initial_regs,
+                                                initial_mem=initial_mem)
+            self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64))
+
+    def run_tst_program(self, prog, initial_regs=None, initial_mem=None):
+        # DO NOT set complex arguments, it is a "singleton" pattern
+        if initial_regs is None:
+            initial_regs = [0] * 32
 
-    def run_tst_program(self, prog, initial_regs=[0] * 32):
         # set up dummy minimal ISACaller
         spr = {'DSISR': SelectableInt(0, 64),
                'DAR': SelectableInt(0, 64),
@@ -64,7 +79,7 @@ class DecoderTestCase(FHDLTestCase):
                'PRTBL': SelectableInt(prtbl, 64)
         }
 
-        simulator = run_tst(prog, initial_regs, mmu=True, mem=testmem,
+        simulator = run_tst(prog, initial_regs, mmu=True, mem=initial_mem,
                     initial_sprs=spr)
         simulator.gpr.dump()
         return simulator