From: Andrey Miroshnikov <andrey@technepisteme.xyz>
Date: Tue, 28 Nov 2023 19:52:17 +0000 (+0000)
Subject: Added prefix proposal 2019 link, thx Jacob
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=59afd733267d46646be8a241c7df950ee2923fe6;p=libreriscv.git

Added prefix proposal 2019 link, thx Jacob
---

diff --git a/meetings/sync_up/sync_up_2023-11-28.mdwn b/meetings/sync_up/sync_up_2023-11-28.mdwn
index 70bed2d9e..19eb54d79 100644
--- a/meetings/sync_up/sync_up_2023-11-28.mdwn
+++ b/meetings/sync_up/sync_up_2023-11-28.mdwn
@@ -23,6 +23,7 @@
 * Clarification of the scope of new grants.
   See [[meetings/dmitry_2023-11-24]] notes for more context.
 
+- SimpleV prefix proposal from 2019: <https://libre-soc.org/simple_v_extension/sv_prefix_proposal/>
 - RISC-V example extension: <https://github.com/riscv-software-src/riscv-isa-sim/blob/master/customext/cflush.cc>
 - The first step is to make modifications to `svanalysis.py` to classify the RISC-V instructions.
 - Standard RISC-V opcode format: <https://github.com/riscv/riscv-opcodes>