From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 19 Jun 2021 12:02:03 +0000 (+0100)
Subject: add decode of "reverse gear" in SVP64 reduce mode
X-Git-Tag: xlen-bcd~429
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=59b33c34210be3284b910556ba367fff7b509a07;p=openpower-isa.git

add decode of "reverse gear" in SVP64 reduce mode
---

diff --git a/src/openpower/decoder/power_svp64_rm.py b/src/openpower/decoder/power_svp64_rm.py
index dad6853b..a91487e1 100644
--- a/src/openpower/decoder/power_svp64_rm.py
+++ b/src/openpower/decoder/power_svp64_rm.py
@@ -97,6 +97,7 @@ class SVP64RMModeDecode(Elaboratable):
         self.inv = Signal(1)     # and whether it's inverted (like branch BO)
         self.map_evm = Signal(1)
         self.map_crm = Signal(1)
+        self.reverse_gear = Signal(1)  # elements to go VL-1..0
         self.ldstmode = Signal(SVP64LDSTmode) # LD/ST Mode (strided type)
 
     def elaborate(self, platform):
@@ -123,6 +124,13 @@ class SVP64RMModeDecode(Elaboratable):
             with m.Case(3):
                 comb += self.mode.eq(SVP64RMMode.PREDRES) # predicate result
 
+        # extract "reverse gear" for mapreduce mode
+        with m.If((~is_ldst) &                     # not for LD/ST
+                    (mode2 == 0) &                 # first 2 bits == 0
+                    mode[SVP64MODE.REDUCE] &       # bit 2 == 1
+                   (~mode[SVP64MODE.PARALLEL])):   # not parallel mapreduce
+            comb += self.reverse_gear.eq(1)        # theeeen finally, whew
+
         # extract zeroing
         with m.Switch(mode2):
             with m.Case(0): # needs further decoding (LDST no mapreduce)