From: Dmitry Selyutin Date: Thu, 7 Sep 2023 20:14:27 +0000 (+0300) Subject: libsvp64: support address operands X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=59c7e7131f572f90d11d2df0e1383b57fd9d3fbf;p=openpower-isa.git libsvp64: support address operands --- diff --git a/src/libsvp64/codegen.py b/src/libsvp64/codegen.py index 748796c5..01d6a1c5 100644 --- a/src/libsvp64/codegen.py +++ b/src/libsvp64/codegen.py @@ -285,7 +285,7 @@ class DisGenSource(Source): def nonzero_handler(span): yield from generic_handler(span, "SVP64_OPERAND_NONZERO") - def signed_handler(span): + def signed_handler(span, flags="SVP64_OPERAND_SIGNED"): mask = f"(UINT32_C(1) << (UINT32_C({len(span)}) - 1))" yield "value = (" with self: @@ -301,9 +301,12 @@ class DisGenSource(Source): yield "-" yield f"{mask}" yield ");" - yield "flags = SVP64_OPERAND_SIGNED;" + yield f"flags = {flags};" self.emit("break;") + def address_handler(span): + yield from signed_handler(span, "(SVP64_OPERAND_ADDRESS | SVP64_OPERAND_SIGNED)") + def gpr_handler(span, pair=False): if not pair: yield from generic_handler(span, "SVP64_OPERAND_GPR") @@ -329,6 +332,7 @@ class DisGenSource(Source): insndb.FPROperand: fpr_handler, insndb.CR3Operand: cr3_handler, insndb.CR5Operand: cr5_handler, + insndb.TargetAddrOperand: address_handler, insndb.SignedOperand: signed_handler, insndb.NonZeroOperand: nonzero_handler, insndb.DynamicOperand: generic_handler, diff --git a/src/libsvp64/svp64.h b/src/libsvp64/svp64.h index d0907a08..e7f397dd 100644 --- a/src/libsvp64/svp64.h +++ b/src/libsvp64/svp64.h @@ -39,6 +39,7 @@ struct svp64_operand { #define SVP64_OPERAND_CR3 (UINT32_C(1) << UINT32_C(4)) #define SVP64_OPERAND_CR5 (UINT32_C(1) << UINT32_C(5)) #define SVP64_OPERAND_NONZERO (UINT32_C(1) << UINT32_C(6)) +#define SVP64_OPERAND_ADDRESS (UINT32_C(1) << UINT32_C(7)) struct svp64_ctx { struct svp64_record const *record;