From: Richard Sandiford <richard.sandiford@arm.com>
Date: Thu, 24 Sep 2020 09:06:11 +0000 (+0100)
Subject: arm: Add a couple of extra stack-protector tests
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=59c8329389751ec39985a89a673768b4d4fdb338;p=gcc.git

arm: Add a couple of extra stack-protector tests

These tests were inspired by corresponding aarch64 ones.
They already pass.

gcc/testsuite/
	* gcc.target/arm/stack-protector-5.c: New test.
	* gcc.target/arm/stack-protector-6.c: Likewise.
---

diff --git a/gcc/testsuite/gcc.target/arm/stack-protector-5.c b/gcc/testsuite/gcc.target/arm/stack-protector-5.c
new file mode 100644
index 00000000000..b808b11aa3d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/stack-protector-5.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-fstack-protector-all -O2" } */
+
+void __attribute__ ((noipa))
+f (void)
+{
+  volatile int x;
+  asm volatile ("" :::
+		"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+		"r8", "r9", "r10", "r11", "r12", "r14");
+}
+
+/* The register clobbers above should not generate any single LDRs or STRs;
+   all registers should be pushed and popped using register lists.  The only
+   STRs should therefore be those associated with the stack protector tests
+   themselves.
+
+   Make sure the address of the canary is not spilled and reloaded,
+   since that would give the attacker an opportunity to change the
+   canary value.  */
+/* { dg-final { scan-assembler-times {\tstr\t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/arm/stack-protector-6.c b/gcc/testsuite/gcc.target/arm/stack-protector-6.c
new file mode 100644
index 00000000000..f8eec878bd6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/stack-protector-6.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-fstack-protector-all -O2 -fpic" } */
+
+#include "stack-protector-5.c"
+
+/* See the comment in stack-protector-5.c.  */
+/* { dg-final { scan-assembler-times {\tstr\t} 1 } } */