From: Cesar Strauss <cestrauss@gmail.com>
Date: Sun, 28 Jun 2020 20:44:10 +0000 (-0300)
Subject: Add missing ports to the test ALU
X-Git-Tag: div_pipeline~213
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=59d08c2c4a036d6cb4881b86a98ce2d6ae459353;p=soc.git

Add missing ports to the test ALU
---

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index 99ff39e4..5b1968c2 100644
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -278,6 +278,10 @@ class ALU(Elaboratable):
         yield self.a
         yield self.b
         yield self.o
+        yield self.p.valid_i
+        yield self.p.ready_o
+        yield self.n.valid_o
+        yield self.n.ready_i
 
     def ports(self):
         return list(self)