From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 10 Jun 2013 11:56:03 +0000 (+0200)
Subject: Fixes and improvements in AST const folding
X-Git-Tag: yosys-0.2.0~585
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=59dd02baa2877e98b377989d22c3657b525bd090;p=yosys.git

Fixes and improvements in AST const folding
---

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 1fb762fc1..c75bca911 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -647,7 +647,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint)
 				current_module->wires[str] = wire;
 			}
 			else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) {
-				chunk = RTLIL::Const(id2ast->bits);
+				chunk = RTLIL::Const(id2ast->children[0]->bits);
 				goto use_const_chunk;
 			}
 			else if (!id2ast || (id2ast->type != AST_WIRE && id2ast->type != AST_AUTOWIRE &&
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 9035d5478..bc135b39d 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -749,6 +749,7 @@ skip_dynamic_range_lvalue_expansion:;
 	// perform const folding when activated
 	if (const_fold && newNode == NULL)
 	{
+		std::vector<RTLIL::State> tmp_bits;
 		RTLIL::Const (*const_func)(const RTLIL::Const&, const RTLIL::Const&, bool, bool, int);
 		RTLIL::Const dummy_arg;
 
@@ -864,7 +865,16 @@ skip_dynamic_range_lvalue_expansion:;
 					newNode = children[2]->clone();
 			}
 			break;
+		case AST_CONCAT:
+			for (auto it = children.begin(); it != children.end(); it++) {
+				if ((*it)->type != AST_CONSTANT)
+					goto not_const;
+				tmp_bits.insert(tmp_bits.end(), (*it)->bits.begin(), (*it)->bits.end());
+			}
+			newNode = mkconst_bits(tmp_bits, is_signed);
+			break;
 		default:
+		not_const:
 			break;
 		}
 	}