From: whitequark <cz@m-labs.hk>
Date: Wed, 2 Oct 2019 03:50:20 +0000 (+0000)
Subject: back.rtlil: sign of rhs and lhs of ${sshr,sshl,pow} don't need to match.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=59dd3466bec4e5bb344255590e517796d829b3be;p=nmigen.git

back.rtlil: sign of rhs and lhs of ${sshr,sshl,pow} don't need to match.
---

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 298d2f9..7424c9d 100644
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -485,7 +485,7 @@ class _RHSValueCompiler(_ValueCompiler):
         lhs, rhs = value.operands
         lhs_bits, lhs_sign = lhs.shape()
         rhs_bits, rhs_sign = rhs.shape()
-        if lhs_sign == rhs_sign:
+        if lhs_sign == rhs_sign or value.op in ("<<", ">>", "**"):
             lhs_wire = self(lhs)
             rhs_wire = self(rhs)
         else: