From: lkcl <lkcl@web>
Date: Tue, 13 Aug 2019 07:26:51 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~4221
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=59e0068db95f30a58dfd97da5e49fd7d36447edf;p=libreriscv.git

---

diff --git a/simple_v_extension/specification/mv.x.rst b/simple_v_extension/specification/mv.x.rst
index f0ed748f1..916445e94 100644
--- a/simple_v_extension/specification/mv.x.rst
+++ b/simple_v_extension/specification/mv.x.rst
@@ -55,3 +55,9 @@ macro-op fusion
 
 there is the potential for macro-op fusion of mv-swizzle with the following instruction and/or preceding instruction.
 <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-August/002486.html>
+
+VBLOCK context?
+===============
+
+additional idea: a VBLOCK context that says that if a given register is used, it indicates that the
+register is to be "swizzled", and the VBLOCK swizzle context contains the swizzling to be carried out.