From: Jeff Law <law@redhat.com>
Date: Mon, 23 Feb 1998 17:29:31 +0000 (+0000)
Subject:         * gas/mips/vr5400.s: Use absolute expression for performance
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=59ef7c27fb9d517a6ac52210da6faa74f219712a;p=binutils-gdb.git

    * gas/mips/vr5400.s: Use absolute expression for performance
        register number.

        * gas/mips/r5900.s: Use absolute expression for performance
        register number.
---

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 62a956f4276..733da0c1dc4 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,4 +1,16 @@
+start-sanitize-vr5400
+Mon Feb 23 10:31:05 1998  Jeffrey A Law  (law@cygnus.com)
+
+        * gas/mips/vr5400.s: Use absolute expression for performance
+        register number.
+
+end-sanitize-vr5400
 start-sanitize-r5900
+Mon Feb 23 10:31:05 1998  Jeffrey A Law  (law@cygnus.com)
+
+        * gas/mips/r5900.s: Use absolute expression for performance
+        register number.
+
 Fri Feb 20 01:29:16 1998  Jeffrey A Law  (law@cygnus.com)
 
 	* gas/mips/r5900.s, gas/mips/r5900.d: Update for "mula.s" change.
diff --git a/gas/testsuite/gas/mips/vr5400.s b/gas/testsuite/gas/mips/vr5400.s
new file mode 100644
index 00000000000..7a6ec8b42b3
--- /dev/null
+++ b/gas/testsuite/gas/mips/vr5400.s
@@ -0,0 +1,121 @@
+	.text
+
+stuff:
+	.ent stuff
+	/* Integer instructions.  */
+
+	mul	$4,$5,$6
+	mulu	$4,$5,$6
+	mulhi	$4,$5,$6
+	mulhiu	$4,$5,$6
+	muls	$4,$5,$6
+	mulsu	$4,$5,$6
+	mulshi	$4,$5,$6
+	mulshiu	$4,$5,$6
+	macc	$4,$5,$6
+	maccu	$4,$5,$6
+	macchi	$4,$5,$6
+	macchiu	$4,$5,$6
+	msac	$4,$5,$6
+	msacu	$4,$5,$6
+	msachi	$4,$5,$6
+	msachiu	$4,$5,$6
+
+	ror	$4,$5,25
+	rorv	$4,$5,$6
+	dror	$4,$5,25
+	dror	$4,$5,57	/* Should expand to dror32 $4,$5,25.  */
+	dror32	$4,$5,25
+	drorv	$4,$5,$6
+
+	/* Debug instructions.  */
+
+	dbreak
+	dret
+	mfdr	$3,$3
+	mtdr	$3,$3
+
+	/* Coprocessor 0 instructions, minus standard ISA 3 ones.
+	   That leaves just the performance monitoring registers.  */
+
+	mfpc	$4,1
+	mfps	$4,1
+	mtpc	$4,1
+	mtps	$4,1
+
+	/* Multimedia instructions.  */
+
+	.macro	nsel2 op
+	/* Test each form of each vector opcode.  */
+	\op	$f0,$f2
+	\op	$f3,$f6[2]
+	\op	$f6,15
+	.if 0	/* Which is right?? */
+	/* Test negative numbers in immediate-value slot.  */
+	\op	$f4,-3
+	.else
+	/* Test that it's recognized as an unsigned field.  */
+	\op	$f3,31
+	.endif
+	.endm
+
+	.macro	nsel3 op
+	/* Test each form of each vector opcode.  */
+	\op	$f0,$f1,$f2
+	\op	$f3,$f4,$f6[2]
+	\op	$f6,$f5,15
+	.if 0	/* Which is right?? */
+	/* Test negative numbers in immediate-value slot.  */
+	\op	$f4,$f6,-3
+	.else
+	/* Test that it's recognized as an unsigned field.  */
+	\op	$f3,$f7,31
+	.endif
+	.endm
+
+	nsel3	add.ob
+	nsel3	and.ob
+	nsel2	c.eq.ob
+	nsel2	c.le.ob
+	nsel2	c.lt.ob
+	nsel3	max.ob
+	nsel3	min.ob
+	nsel3	mul.ob
+	nsel2	mula.ob
+	nsel2	mull.ob
+	nsel2	muls.ob
+	nsel2	mulsl.ob
+	nsel3	nor.ob
+	nsel3	or.ob
+	nsel3	pickf.ob
+	nsel3	pickt.ob
+	nsel3	sub.ob
+	nsel3	xor.ob
+
+	/* ALNI, SHFL: Vector only.  */
+	alni.ob		$f1,$f2,$f3,5
+	shfl.mixh.ob	$f1,$f2,$f3
+	shfl.mixl.ob	$f1,$f2,$f3
+	shfl.pach.ob	$f1,$f2,$f3
+	shfl.pacl.ob	$f1,$f2,$f3
+
+	/* SLL,SRL: Scalar or immediate.  */
+	sll.ob	$f2,$f4,$f5[3]
+	sll.ob	$f3,$f6,14
+	srl.ob	$f2,$f4,$f5[3]
+	srl.ob	$f3,$f6,14
+
+	/* RZU: Immediate, must be 0, 8, or 16.  */
+	rzu.ob	$f2,13
+
+	/* No selector.  */
+	rach.ob	$f2
+	racl.ob	$f2
+	racm.ob	$f2
+	wach.ob	$f2
+	wacl.ob	$f2,$f3
+
+	/* Align to 16-byte boundary.  */
+	nop
+	nop
+	nop