From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 18 Sep 2022 20:32:14 +0000 (+0100)
Subject: bit of a hack-job, a base class MRBaseRM - MapReduce RM - was confused
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5a0156ad0725ab59c4c5af298f110629857fb847;p=openpower-isa.git

bit of a hack-job, a base class MRBaseRM - MapReduce RM - was confused
there is no need to report "/mr" on a "Simple" mode, which was deriving
from MRBaseRM
---

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index 47ee25eb..e9f172f9 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1364,9 +1364,15 @@ class SZBaseRM(BaseRM):
 class MRBaseRM(BaseRM):
     def specifiers(self, record):
         if self.RG:
-            yield "mrr"
+            # reverse-gear but this is a mix-in class, different reports needed
+            if isinstance(self, CROpSimpleRM):
+                yield "rg" # simple CR Mode reports /rg
+            else:
+                yield "mrr" # all others assume "mapreduce+reverse"
         else:
-            yield "mr"
+            # in CR-Simple just don't report anything
+            if not isinstance(self, CROpSimpleRM):
+                yield "mr" # all but CR-Simple report "mapreduce"
 
         yield from super().specifiers(record=record)