From: Rhys Perry <pendingchaos02@gmail.com>
Date: Tue, 12 Nov 2019 15:44:17 +0000 (+0000)
Subject: aco: fix read_invocation with VGPR lane index
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5a1bacb6f916d9a46a3d44830a4eb4bd3dca7d23;p=mesa.git

aco: fix read_invocation with VGPR lane index

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler')
---

diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index f616da9d88d..cdedb516542 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -5626,9 +5626,8 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
    }
    case nir_intrinsic_read_invocation: {
       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
-      Temp lane = get_ssa_temp(ctx, instr->src[1].ssa);
+      Temp lane = bld.as_uniform(get_ssa_temp(ctx, instr->src[1].ssa));
       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
-      assert(lane.regClass() == s1);
       if (src.regClass() == v1) {
          emit_wqm(ctx, bld.vop3(aco_opcode::v_readlane_b32, bld.def(s1), src, lane), dst);
       } else if (src.regClass() == v2) {