From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 22 Nov 2019 00:15:25 +0000 (-0800)
Subject: Merge branch 'eddie/xaig_dff_adff' into xaig_dff
X-Git-Tag: working-ls180~881^2^2~160
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5a30e3ac3ba6435ebf9db0f8acfba61e9ee73ad7;p=yosys.git

Merge branch 'eddie/xaig_dff_adff' into xaig_dff
---

5a30e3ac3ba6435ebf9db0f8acfba61e9ee73ad7
diff --cc tests/simple_abc9/abc9.v
index 13c505eec,58596d701..596a52501
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@@ -268,12 -268,14 +268,23 @@@ assign o = { 1'b1, 1'bx }
  assign p = { 1'b1, 1'bx, 1'b0 };
  endmodule
  
- module abc9_test029(input clk1, clk2, d, output reg q1, q2);
+ module abc9_test029(input clk, d, r, output reg q);
+ always @(posedge clk or posedge r)
+     if (r) q <= 1'b0;
+     else q <= d;
+ endmodule
+ 
+ module abc9_test030(input clk, d, r, output reg q);
+ always @(negedge clk or posedge r)
+     if (r) q <= 1'b1;
+     else q <= d;
+ endmodule
++
++module abc9_test032(input clk1, clk2, d, output reg q1, q2);
 +always @(posedge clk1) q1 <= d;
 +always @(negedge clk2) q2 <= q1;
 +endmodule
 +
- module abc9_test030(input clk, d, output reg q1, q2);
++module abc9_test033(input clk, d, output reg q1, q2);
 +always @(posedge clk) q1 <= d;
 +always @(posedge clk) q2 <= q1;
- endmodule