From: Mike Frysinger <vapier@gentoo.org>
Date: Mon, 6 Dec 2021 07:10:27 +0000 (-0500)
Subject: sim: riscv: migrate to standard uintXX_t types
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5a33ead2d35e4195147e9befe9e18addfa2abcd2;p=binutils-gdb.git

sim: riscv: migrate to standard uintXX_t types

Move off the sim-specific unsignedXX types and to the standard uintXX_t
types that C11 provides.
---

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 7b672f6a91d..62f475671c9 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -131,14 +131,14 @@ store_csr (SIM_CPU *cpu, const char *name, int csr, unsigned_word *reg,
 static inline unsigned_word
 ashiftrt (unsigned_word val, unsigned_word shift)
 {
-  unsigned32 sign = (val & 0x80000000) ? ~(0xfffffffful >> shift) : 0;
+  uint32_t sign = (val & 0x80000000) ? ~(0xfffffffful >> shift) : 0;
   return (val >> shift) | sign;
 }
 
 static inline unsigned_word
 ashiftrt64 (unsigned_word val, unsigned_word shift)
 {
-  unsigned64 sign =
+  uint64_t sign =
     (val & 0x8000000000000000ull) ? ~(0xffffffffffffffffull >> shift) : 0;
   return (val >> shift) | sign;
 }
@@ -155,7 +155,7 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
   const char *rs2_name = riscv_gpr_names_abi[rs2];
   unsigned int csr = (iw >> OP_SH_CSR) & OP_MASK_CSR;
   unsigned_word i_imm = EXTRACT_ITYPE_IMM (iw);
-  unsigned_word u_imm = EXTRACT_UTYPE_IMM ((unsigned64) iw);
+  unsigned_word u_imm = EXTRACT_UTYPE_IMM ((uint64_t) iw);
   unsigned_word s_imm = EXTRACT_STYPE_IMM (iw);
   unsigned_word sb_imm = EXTRACT_BTYPE_IMM (iw);
   unsigned_word shamt_imm = ((iw >> OP_SH_SHAMT) & OP_MASK_SHAMT);
@@ -252,7 +252,7 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
       RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
       store_rd (cpu, rd, EXTEND32 (
-	(unsigned32) cpu->regs[rs1] << (cpu->regs[rs2] & 0x1f)));
+	(uint32_t) cpu->regs[rs1] << (cpu->regs[rs2] & 0x1f)));
       break;
     case MATCH_SLLI:
       TRACE_INSN (cpu, "slli %s, %s, %" PRIiTW ";  // %s = %s << %#" PRIxTW,
@@ -265,7 +265,7 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       TRACE_INSN (cpu, "slliw %s, %s, %" PRIiTW ";  // %s = %s << %#" PRIxTW,
 		  rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
       RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
-      store_rd (cpu, rd, EXTEND32 ((unsigned32) cpu->regs[rs1] << shamt_imm));
+      store_rd (cpu, rd, EXTEND32 ((uint32_t) cpu->regs[rs1] << shamt_imm));
       break;
     case MATCH_SRL:
       TRACE_INSN (cpu, "srl %s, %s, %s;  // %s = %s >> %s",
@@ -278,7 +278,7 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
       RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
       store_rd (cpu, rd, EXTEND32 (
-	(unsigned32) cpu->regs[rs1] >> (cpu->regs[rs2] & 0x1f)));
+	(uint32_t) cpu->regs[rs1] >> (cpu->regs[rs2] & 0x1f)));
       break;
     case MATCH_SRLI:
       TRACE_INSN (cpu, "srli %s, %s, %" PRIiTW ";  // %s = %s >> %#" PRIxTW,
@@ -291,7 +291,7 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       TRACE_INSN (cpu, "srliw %s, %s, %" PRIiTW ";  // %s = %s >> %#" PRIxTW,
 		  rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
       RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
-      store_rd (cpu, rd, EXTEND32 ((unsigned32) cpu->regs[rs1] >> shamt_imm));
+      store_rd (cpu, rd, EXTEND32 ((uint32_t) cpu->regs[rs1] >> shamt_imm));
       break;
     case MATCH_SRA:
       TRACE_INSN (cpu, "sra %s, %s, %s;  // %s = %s >>> %s",
@@ -307,7 +307,7 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
       RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
       store_rd (cpu, rd, EXTEND32 (
-	ashiftrt ((signed32) cpu->regs[rs1], cpu->regs[rs2] & 0x1f)));
+	ashiftrt ((int32_t) cpu->regs[rs1], cpu->regs[rs2] & 0x1f)));
       break;
     case MATCH_SRAI:
       TRACE_INSN (cpu, "srai %s, %s, %" PRIiTW ";  // %s = %s >>> %#" PRIxTW,
@@ -327,7 +327,7 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 		  rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
       RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
       store_rd (cpu, rd, EXTEND32 (
-	ashiftrt ((signed32) cpu->regs[rs1], shamt_imm)));
+	ashiftrt ((int32_t) cpu->regs[rs1], shamt_imm)));
       break;
     case MATCH_SLT:
       TRACE_INSN (cpu, "slt");
@@ -600,8 +600,8 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
   return pc;
 }
 
-static unsigned64
-mulhu (unsigned64 a, unsigned64 b)
+static uint64_t
+mulhu (uint64_t a, uint64_t b)
 {
 #ifdef HAVE___INT128
   return ((__int128)a * b) >> 64;
@@ -626,16 +626,16 @@ mulhu (unsigned64 a, unsigned64 b)
 #endif
 }
 
-static unsigned64
-mulh (signed64 a, signed64 b)
+static uint64_t
+mulh (int64_t a, int64_t b)
 {
   int negate = (a < 0) != (b < 0);
   uint64_t res = mulhu (a < 0 ? -a : a, b < 0 ? -b : b);
   return negate ? ~res + (a * b == 0) : res;
 }
 
-static unsigned64
-mulhsu (signed64 a, unsigned64 b)
+static uint64_t
+mulhsu (int64_t a, uint64_t b)
 {
   int negate = a < 0;
   uint64_t res = mulhu (a < 0 ? -a : a, b);
@@ -695,8 +695,8 @@ execute_m (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       TRACE_INSN (cpu, "divuw %s, %s, %s;  // %s = %s / %s",
 		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
       RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
-      if ((unsigned32) cpu->regs[rs2])
-	tmp = (unsigned32) cpu->regs[rs1] / (unsigned32) cpu->regs[rs2];
+      if ((uint32_t) cpu->regs[rs2])
+	tmp = (uint32_t) cpu->regs[rs1] / (uint32_t) cpu->regs[rs2];
       else
 	tmp = -1;
       store_rd (cpu, rd, EXTEND32 (tmp));
@@ -710,15 +710,15 @@ execute_m (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       TRACE_INSN (cpu, "mulw %s, %s, %s;  // %s = %s * %s",
 		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
       RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
-      store_rd (cpu, rd, EXTEND32 ((signed32) cpu->regs[rs1]
-				   * (signed32) cpu->regs[rs2]));
+      store_rd (cpu, rd, EXTEND32 ((int32_t) cpu->regs[rs1]
+				   * (int32_t) cpu->regs[rs2]));
       break;
     case MATCH_MULH:
       TRACE_INSN (cpu, "mulh %s, %s, %s;  // %s = %s * %s",
 		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
       if (RISCV_XLEN (cpu) == 32)
-	store_rd (cpu, rd, ((signed64)(signed_word) cpu->regs[rs1]
-			    * (signed64)(signed_word) cpu->regs[rs2]) >> 32);
+	store_rd (cpu, rd, ((int64_t)(signed_word) cpu->regs[rs1]
+			    * (int64_t)(signed_word) cpu->regs[rs2]) >> 32);
       else
 	store_rd (cpu, rd, mulh (cpu->regs[rs1], cpu->regs[rs2]));
       break;
@@ -726,8 +726,8 @@ execute_m (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       TRACE_INSN (cpu, "mulhu %s, %s, %s;  // %s = %s * %s",
 		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
       if (RISCV_XLEN (cpu) == 32)
-	store_rd (cpu, rd, ((unsigned64)cpu->regs[rs1]
-			    * (unsigned64)cpu->regs[rs2]) >> 32);
+	store_rd (cpu, rd, ((uint64_t)cpu->regs[rs1]
+			    * (uint64_t)cpu->regs[rs2]) >> 32);
       else
 	store_rd (cpu, rd, mulhu (cpu->regs[rs1], cpu->regs[rs2]));
       break;
@@ -735,8 +735,8 @@ execute_m (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       TRACE_INSN (cpu, "mulhsu %s, %s, %s;  // %s = %s * %s",
 		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
       if (RISCV_XLEN (cpu) == 32)
-	store_rd (cpu, rd, ((signed64)(signed_word) cpu->regs[rs1]
-			    * (unsigned64)cpu->regs[rs2]) >> 32);
+	store_rd (cpu, rd, ((int64_t)(signed_word) cpu->regs[rs1]
+			    * (uint64_t)cpu->regs[rs2]) >> 32);
       else
 	store_rd (cpu, rd, mulhsu (cpu->regs[rs1], cpu->regs[rs2]));
       break;
@@ -775,8 +775,8 @@ execute_m (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       TRACE_INSN (cpu, "remuw %s, %s, %s;  // %s = %s %% %s",
 		  rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
       RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
-      if ((unsigned32) cpu->regs[rs2])
-	tmp = (unsigned32) cpu->regs[rs1] % (unsigned32) cpu->regs[rs2];
+      if ((uint32_t) cpu->regs[rs2])
+	tmp = (uint32_t) cpu->regs[rs1] % (uint32_t) cpu->regs[rs2];
       else
 	tmp = cpu->regs[rs1];
       store_rd (cpu, rd, EXTEND32 (tmp));
@@ -1113,7 +1113,7 @@ initialize_cpu (SIM_DESC sd, SIM_CPU *cpu, int mhartid)
   cpu->csr.misa = 0;
   /* RV32 sets this field to 0, and we don't really support RV128 yet.  */
   if (RISCV_XLEN (cpu) == 64)
-    cpu->csr.misa |= (unsigned64)2 << 62;
+    cpu->csr.misa |= (uint64_t)2 << 62;
 
   /* Skip the leading "rv" prefix and the two numbers.  */
   extensions = MODEL_NAME (CPU_MODEL (cpu)) + 4;