From: lkcl Date: Sun, 25 Jul 2021 13:21:28 +0000 (+0100) Subject: (no commit message) X-Git-Tag: DRAFT_SVP64_0_1~589 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5a3c61fa82048b276691cf42aa3ce234508c9fad;p=libreriscv.git --- diff --git a/conferences/xdc2021.mdwn b/conferences/xdc2021.mdwn index 02d5dbb29..807290022 100644 --- a/conferences/xdc2021.mdwn +++ b/conferences/xdc2021.mdwn @@ -4,6 +4,9 @@ # Abstract +Author: +Luke Leighton +The Libre-SOC Project is an initiative to create an entirely Libre Hybrid 3D CPU-VPU-GPU. Critical to that is to have decent Vectorisation support. Most GPUs use predicated SIMD: SIMD has been demonstrated multiple times to be harmful, and with Libre-SOC also needing to run standard CPU workloads as well, designing an ISA and associated compilers and toolcgains was impractical. Therefore a Vector ISA has been designed which, in effect, uses the x86-style "REP" instruction on top of the scalar Power ISA v3.0. The key motivation here is that by reducing executable size, power consumption and latency are reduced, which is important given that the three separate workloads for CPU, VPU and 3D GPU will all be covered by the same core.