From: Eddie Hung <eddie@fpgeh.com>
Date: Sun, 29 Sep 2019 16:58:00 +0000 (-0700)
Subject: Fix "scc" call inside abc9 to consider all wires
X-Git-Tag: working-ls180~881^2^2~204
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5a4011e8c9d2c7c94ccaa6ff80a1ca1290e1053b;p=yosys.git

Fix "scc" call inside abc9 to consider all wires
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index a5d823139..ce27f7eea 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -75,7 +75,7 @@ inline std::string remap_name(RTLIL::IdString abc_name)
 
 void handle_loops(RTLIL::Design *design)
 {
-	Pass::call(design, "scc -set_attr abc_scc_id {}");
+	Pass::call(design, "scc -set_attr abc_scc_id {} % w:*");
 
 	// For every unique SCC found, (arbitrarily) find the first
 	// cell in the component, and select (and mark) all its output