From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 7 Jun 2019 23:57:32 +0000 (-0700)
Subject: Fine tune aigerparse
X-Git-Tag: working-ls180~1208^2~179
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5a46a0b38584014c3644cc434458638874bd4d75;p=yosys.git

Fine tune aigerparse
---

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 20b43c3d3..4c19ec171 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -85,21 +85,10 @@ end_of_header:
 	else
 		log_abort();
 
-	RTLIL::Wire* n0 = module->wire("\\n0");
+	RTLIL::Wire* n0 = module->wire("\\__0__");
 	if (n0)
 		module->connect(n0, RTLIL::S0);
 
-	for (unsigned i = 0; i < outputs.size(); ++i) {
-		RTLIL::Wire *wire = outputs[i];
-		if (wire->port_input) {
-			RTLIL::Wire *o_wire = module->addWire(wire->name.str() + "_o");
-			o_wire->port_output = true;
-			wire->port_output = false;
-			module->connect(o_wire, wire);
-			outputs[i] = o_wire;
-		}
-	}
-
 	// Parse footer (symbol table, comments, etc.)
 	unsigned l1;
 	std::string s;
@@ -212,6 +201,10 @@ void AigerReader::parse_xaiger()
 	else
 		log_abort();
 
+	RTLIL::Wire* n0 = module->wire("\\__0__");
+	if (n0)
+		module->connect(n0, RTLIL::S0);
+
 	dict<int,IdString> box_lookup;
 	for (auto m : design->modules()) {
 		auto it = m->attributes.find("\\abc_box_id");
@@ -386,31 +379,17 @@ void AigerReader::parse_aiger_ascii()
 		if (!(f >> l1))
 			log_error("Line %u cannot be interpreted as an output!\n", line_count);
 
-		RTLIL::Wire *wire;
-		if (l1 == 0 || l1 == 1) {
-			wire = module->addWire(NEW_ID);
-			if (l1 == 0)
-				module->connect(wire, RTLIL::State::S0);
-			else if (l1 == 1)
-				module->connect(wire, RTLIL::State::S1);
-			else
-				log_abort();
-		}
-		else {
-			log_debug("%d is an output\n", l1);
-			const unsigned variable = l1 >> 1;
-			const bool invert = l1 & 1;
-			RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "b" the right suffix?
-			wire = module->wire(wire_name);
-			if (!wire)
-				wire = createWireIfNotExists(module, l1);
-			else {
-				if (wire->port_input || wire->port_output) {
-					RTLIL::Wire *new_wire = module->addWire(NEW_ID);
-					module->connect(new_wire, wire);
-					wire = new_wire;
-				}
-			}
+		log_debug("%d is an output\n", l1);
+		const unsigned variable = l1 >> 1;
+		const bool invert = l1 & 1;
+		RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "b" the right suffix?
+		RTLIL::Wire *wire = module->wire(wire_name);
+		if (!wire)
+			wire = createWireIfNotExists(module, l1);
+		else if (wire->port_input || wire->port_output) {
+			RTLIL::Wire *new_wire = module->addWire(NEW_ID);
+			module->connect(new_wire, wire);
+			wire = new_wire;
 		}
 		wire->port_output = true;
 		outputs.push_back(wire);
@@ -525,31 +504,17 @@ void AigerReader::parse_aiger_binary()
 		if (!(f >> l1))
 			log_error("Line %u cannot be interpreted as an output!\n", line_count);
 
-		RTLIL::Wire *wire;
-		if (l1 == 0 || l1 == 1) {
-			wire = module->addWire(NEW_ID);
-			if (l1 == 0)
-				module->connect(wire, RTLIL::State::S0);
-			else if (l1 == 1)
-				module->connect(wire, RTLIL::State::S1);
-			else
-				log_abort();
-		}
-		else {
-			log_debug("%d is an output\n", l1);
-			const unsigned variable = l1 >> 1;
-			const bool invert = l1 & 1;
-			RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "_b" the right suffix?
-			wire = module->wire(wire_name);
-			if (!wire)
-				wire = createWireIfNotExists(module, l1);
-			else {
-				if (wire->port_input || wire->port_output) {
-					RTLIL::Wire *new_wire = module->addWire(NEW_ID);
-					module->connect(new_wire, wire);
-					wire = new_wire;
-				}
-			}
+		log_debug("%d is an output\n", l1);
+		const unsigned variable = l1 >> 1;
+		const bool invert = l1 & 1;
+		RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "_b" the right suffix?
+		RTLIL::Wire *wire = module->wire(wire_name);
+		if (!wire)
+			wire = createWireIfNotExists(module, l1);
+		else if (wire->port_input || wire->port_output) {
+			RTLIL::Wire *new_wire = module->addWire(NEW_ID);
+			module->connect(new_wire, wire);
+			wire = new_wire;
 		}
 		wire->port_output = true;
 		outputs.push_back(wire);
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 06a638558..af9439e41 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -586,7 +586,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 					RTLIL::Cell *cell;
 					RTLIL::SigBit a_bit = c->getPort("\\A").as_bit();
 					RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit();
-					if (!lut_costs.empty() || !lut_file.empty()) {
+					if (!a_bit.wire) {
+						c->setPort("\\Y", module->addWire(NEW_ID));
+						module->connect(module->wires_[remap_name(y_bit.wire->name)], RTLIL::S1);
+					}
+					else if (!lut_costs.empty() || !lut_file.empty()) {
 						RTLIL::Cell* driving_lut = nullptr;
 						// ABC can return NOT gates that drive POs
 						if (!a_bit.wire->port_input) {