From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 5 Jul 2019 10:27:44 +0000 (+0100)
Subject: identify points where DivPipeCore*Data is needed
X-Git-Tag: ls180-24jan2020~928
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5a5ec7e41797a577b7995fb0a6fd9629d19b5015;p=ieee754fpu.git

identify points where DivPipeCore*Data is needed
---

diff --git a/src/ieee754/fpdiv/div1.py b/src/ieee754/fpdiv/div1.py
index dd2aba48..27e4b782 100644
--- a/src/ieee754/fpdiv/div1.py
+++ b/src/ieee754/fpdiv/div1.py
@@ -9,7 +9,7 @@ from nmigen.cli import main, verilog
 from ieee754.fpcommon.fpbase import FPNumBaseRecord
 from ieee754.fpcommon.fpbase import FPState
 from ieee754.fpcommon.denorm import FPSCData
-from .div0 import FPDivStage0Data
+from .div0 import FPDivStage0Data # TODO: replace with DivPipeCoreInterstageData
 
 
 class FPDivStage1Mod(Elaboratable):
@@ -21,9 +21,11 @@ class FPDivStage1Mod(Elaboratable):
         self.o = self.ospec()
 
     def ispec(self):
+        # TODO: DivPipeCoreInterstageData, here
         return FPDivStage0Data(self.width, self.pspec) # Q/Rem (etc) in...
 
     def ospec(self):
+        # TODO: DivPipeCoreInterstageData, here
         return FPDivStage0Data(self.width, self.pspec) # ... Q/Rem (etc) out
 
     def process(self, i):
diff --git a/src/ieee754/fpdiv/div2.py b/src/ieee754/fpdiv/div2.py
index 9c77667a..43153fc9 100644
--- a/src/ieee754/fpdiv/div2.py
+++ b/src/ieee754/fpdiv/div2.py
@@ -8,7 +8,7 @@ from nmigen.cli import main, verilog
 
 from ieee754.fpcommon.fpbase import FPState
 from ieee754.fpcommon.postcalc import FPAddStage1Data
-from .div0 import FPDivStage0Data
+from .div0 import FPDivStage0Data # XXX TODO: replace
 
 
 class FPDivStage2Mod(FPState, Elaboratable):
@@ -22,9 +22,12 @@ class FPDivStage2Mod(FPState, Elaboratable):
         self.o = self.ospec()
 
     def ispec(self):
+        # TODO: DivPipeCoreInterstageData
         return FPDivStage0Data(self.width, self.pspec) # Q/Rem in...
 
     def ospec(self):
+        # XXX REQUIRED.  MUST NOT BE CHANGED.  this is the format
+        # required for ongoing processing (normalisation, correction etc.)
         return FPAddStage1Data(self.width, self.pspec) # out to post-process
 
     def process(self, i):
diff --git a/src/ieee754/fpdiv/divstages.py b/src/ieee754/fpdiv/divstages.py
index 2dac2a62..d62db0de 100644
--- a/src/ieee754/fpdiv/divstages.py
+++ b/src/ieee754/fpdiv/divstages.py
@@ -33,13 +33,29 @@ class FPDivStages(FPState, SimpleHandshake):
         self.m1o = self.ospec()
 
     def ispec(self):
-        if self.begin:
+        if self.begin: # TODO - this is for FPDivStage0Mod
+            # REQUIRED.  do NOT change.
             return FPSCData(self.width, self.pspec, False) # from denorm
+
+        if self.end: # TODO - this is for FPDivStage2Mod
+            # XXX TODO: replace with "intermediary" (DivPipeCoreInterstageData?)
+            return FPDivStage0Data(self.width, self.pspec) # DIV ispec (loop)
+
+        # TODO - this is for FPDivStage1Mod
+        # XXX TODO: replace with "intermediary" (DivPipeCoreInterstageData)
         return FPDivStage0Data(self.width, self.pspec) # DIV ispec (loop)
 
     def ospec(self):
-        if self.end: # TODO
+        if self.begin: # TODO - this is for FPDivStage0Mod
+            # XXX TODO: replace with "intermediary" (DivPipeCoreInterstageData)
+            return FPDivStage0Data(self.width, self.pspec) # DIV ospec (loop)
+
+        if self.end: # TODO - this is for FPDivStage2Mod
+            # REQUIRED.  do NOT change.
             return FPAddStage1Data(self.width, self.pspec) # to post-norm
+
+        # TODO - this is for FPDivStage1Mod
+        # XXX TODO: replace with "intermediary" (DivPipeCoreInterstageData)
         return FPDivStage0Data(self.width, self.pspec) # DIV ospec (loop)
 
     def setup(self, m, i):