From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 1 Mar 2020 15:40:02 +0000 (+0000)
Subject: correction on single bit flags
X-Git-Tag: div_pipeline~1797
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5a7038bff91539df44f2b4761473e1240bda19d2;p=soc.git

correction on single bit flags
---

diff --git a/src/decoder/power_decoder.py b/src/decoder/power_decoder.py
index 213ab3e2..1f77842e 100644
--- a/src/decoder/power_decoder.py
+++ b/src/decoder/power_decoder.py
@@ -40,7 +40,7 @@ class PowerOp:
                ]
         for bit in single_bit_flags:
             sig = getattr(self, get_signal_name(bit))
-            res.append(sig.eq(0))
+            res.append(sig.eq(int(row.get(bit, 0))))
         return res
 
     def ports(self):