From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 27 May 2020 00:34:31 +0000 (+0100)
Subject: added XER and CR regfiles, using new VirtualRegPort
X-Git-Tag: div_pipeline~805
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5aa0ed5af2359e0e0e0014e803b327b5b3f61650;p=soc.git

added XER and CR regfiles, using new VirtualRegPort
---

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index d6f3a8dd..15ddc7ca 100644
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -3,15 +3,16 @@
 
 Defines the following register files:
 
-    * INT regfile
-    * SPR regfile
-    * CR regfile
-    * XER regfile
-    * FAST regfile
+    * INT regfile   - 32x 64-bit
+    * SPR regfile   - 110x 64-bit
+    * CR regfile    - CR0-7
+    * XER regfile   - XER.so, XER.ca/ca32, XER.ov/ov32
+    * FAST regfile  - PC, MSR, CTR, LR, TAR, SRR1, SRR2
 
 Links:
 
 * https://bugs.libre-soc.org/show_bug.cgi?id=345
+* https://bugs.libre-soc.org/show_bug.cgi?id=351
 * https://libre-soc.org/3d_gpu/architecture/regfile/
 * https://libre-soc.org/openpower/isatables/sprs.csv
 """
@@ -19,6 +20,7 @@ Links:
 # TODO
 
 from soc.regfile import RegFile, RegFileArray
+from soc.regfile.virtual_port import VirtualRegPort
 from soc.decoder.power_enums import SPR
 
 
@@ -40,18 +42,41 @@ class IntRegs(RegFileArray):
 
 
 # CR Regfile
-class CRRegs(RegFileArray):
+class CRRegs(VirtualRegPort):
     """Condition Code Registers (CR0-7)
 
     * QTY 8of 8-bit registers
-    * 8R8W (!) with additional 1R1W for the "full" width
+    * 3R1W 4-bit-wide with additional 1R1W for the "full" 32-bit width
     * Array-based unary-indexed (not binary-indexed)
     * write-through capability (read on same cycle as write)
     """
     def __init__(self):
-        super().__init__(4, 8)
-        self.w_ports = [self.write_port("dest")]
-        self.r_ports = [self.write_port("src1"),
+        super().__init__(32, 8)
+        self.w_ports = [self.full_wr, # 32-bit wide (masked, 8-en lines)
+                        self.write_port("dest")] # 4-bit wide, unary-indexed
+        self.r_ports = [self.full_rd, # 32-bit wide (masked, 8-en lines)
+                        self.write_port("src1"),
+                        self.write_port("src2"),
+                        self.write_port("src3")]
+
+
+# XER Regfile
+class XERRegs(VirtualRegPort):
+    """XER Registers (SO, CA/CA32, OV/OV32)
+
+    * QTY 3of 2-bit registers
+    * 3R3W 2-bit-wide with additional 1R1W for the "full" 6-bit width
+    * Array-based unary-indexed (not binary-indexed)
+    * write-through capability (read on same cycle as write)
+    """
+    def __init__(self):
+        super().__init__(6, 2)
+        self.w_ports = [self.full_wr, # 6-bit wide (masked, 3-en lines)
+                        self.write_port("dest1"),
+                        self.write_port("dest2",
+                        self.write_port("dest3")]
+        self.r_ports = [self.full_rd, # 6-bit wide (masked, 3-en lines)
+                        self.write_port("src1"),
                         self.write_port("src2"),
                         self.write_port("src3")]