From: Diego H <diego@symbioticeda.com>
Date: Mon, 2 Sep 2019 22:43:27 +0000 (-0500)
Subject: Updating gowin
X-Git-Tag: working-ls180~956^2~33^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5aa8d7ceeb663be24c7b815822d0de2ee25431a6;p=yosys.git

Updating gowin
---

diff --git a/techlibs/gowin/arith_map.v b/techlibs/gowin/arith_map.v
index e15de6423..af805b254 100644
--- a/techlibs/gowin/arith_map.v
+++ b/techlibs/gowin/arith_map.v
@@ -45,7 +45,7 @@ module _80_gw1n_alu(A, B, CI, BI, X, Y, CO);
 
    genvar 		i;
    generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
-      ALU #(.ALU_MODE(32'b0))
+      ALU #(.ALU_MODE(0))
       alu(.I0(AA[i]),
 	  .I1(BB[i]),
 	  .I3(1'b0),
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index ac3dbfb29..1fc029e3c 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -226,7 +226,7 @@ struct SynthGowinPass : public ScriptPass
 		if (check_label("vout"))
 		{
 			if (!vout_file.empty() || help_mode)
-				run(stringf("write_verilog -nodec -attr2comment -defparam -renameprefix gen %s",
+				 run(stringf("write_verilog -nohex -decimal -attr2comment -defparam -renameprefix gen %s",
 						help_mode ? "<file-name>" : vout_file.c_str()));
 		}
 	}