From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 16 Aug 2019 23:38:49 +0000 (-0700)
Subject: Use ID()
X-Git-Tag: working-ls180~1123^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5abe133323b2a6a46959f796c4730b2d70cdea26;p=yosys.git

Use ID()
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 8e25d3404..4cdd392b5 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -1086,16 +1086,16 @@ struct Abc9Pass : public Pass {
 				auto w = m->wire(p);
 				log_assert(w);
 				if (w->port_input) {
-					if (w->attributes.count("\\abc_scc_break"))
+					if (w->attributes.count(ID(abc_scc_break)))
 						scc_break_inputs[m->name].insert(p);
-					if (w->attributes.count("\\abc_carry_in")) {
+					if (w->attributes.count(ID(abc_carry_in))) {
 						if (carry_in)
 							log_error("Module '%s' contains more than one 'abc_carry_in' port.\n", log_id(m));
 						carry_in = w;
 					}
 				}
 				if (w->port_output) {
-					if (w->attributes.count("\\abc_carry_out")) {
+					if (w->attributes.count(ID(abc_carry_out))) {
 						if (carry_out)
 							log_error("Module '%s' contains more than one 'abc_carry_out' port.\n", log_id(m));
 						carry_out = w;