From: Florent Kermarrec Date: Thu, 26 Feb 2015 18:01:22 +0000 (+0100) Subject: gensoc: get platform_id from platform X-Git-Tag: 24jan2021_ls180~2597^2~2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5ac5ffe359c059954a4f015e5efce890e769f0e1;p=litex.git gensoc: get platform_id from platform --- diff --git a/misoclib/gensoc/__init__.py b/misoclib/gensoc/__init__.py index 9d490ccf..d812da97 100644 --- a/misoclib/gensoc/__init__.py +++ b/misoclib/gensoc/__init__.py @@ -1,6 +1,5 @@ import os from operator import itemgetter -from collections import defaultdict from math import ceil from migen.fhdl.std import * @@ -26,12 +25,6 @@ class GenSoC(Module): "uart": 0, "timer0": 1, } - known_platform_id = defaultdict(lambda: 0x554E, { - "mixxeo": 0x4D58, - "m1": 0x4D31, - "papilio_pro": 0x5050, - "kc705": 0x4B37 - }) def __init__(self, platform, clk_freq, cpu_reset_address, sram_size=4096, l2_size=0, with_uart=True, cpu_type="lm32", csr_data_width=8, csr_address_width=14): @@ -69,7 +62,8 @@ class GenSoC(Module): # CSR if with_uart: self.submodules.uart = uart.UART(platform.request("serial"), clk_freq, baud=115200) - self.submodules.identifier = identifier.Identifier(self.known_platform_id[platform.name], int(clk_freq), + platform_id = 0x554E if not hasattr(platform, "identifier") else platform.identifier + self.submodules.identifier = identifier.Identifier(platform_id, int(clk_freq), log2_int(l2_size) if l2_size else 0) self.submodules.timer0 = timer.Timer()