From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 28 Mar 2019 13:41:58 +0000 (+0000)
Subject: move PriorityCombMuxInPipe to multipipe
X-Git-Tag: ls180-24jan2020~1436
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5acbc8a418d9984ac37020f071df3a0f41596b4b;p=ieee754fpu.git

move PriorityCombMuxInPipe to multipipe
---

diff --git a/src/add/multipipe.py b/src/add/multipipe.py
index b174cf6b..2f54c471 100644
--- a/src/add/multipipe.py
+++ b/src/add/multipipe.py
@@ -302,18 +302,18 @@ class InputPriorityArbiter:
 
 
 
-class ExamplePipeline(CombMultiInPipeline):
+class PriorityCombMuxInPipe(CombMultiInPipeline):
     """ an example of how to use the combinatorial pipeline.
     """
 
-    def __init__(self, p_len=2):
+    def __init__(self, stage, p_len=2):
         p_mux = InputPriorityArbiter(self, p_len)
-        CombMultiInPipeline.__init__(self, ExampleStage, p_len, p_mux)
+        CombMultiInPipeline.__init__(self, stage, p_len, p_mux)
 
 
 if __name__ == '__main__':
 
-    dut = ExamplePipeline()
+    dut = PriorityCombMuxInPipe(ExampleStage)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_combpipe.il", "w") as f:
         f.write(vl)
diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 3fa5b445..865783a9 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -11,7 +11,7 @@ from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
 from fpbase import MultiShiftRMerge, Trigger
 from singlepipe import (ControlBase, StageChain, UnbufferedPipeline)
 from multipipe import CombMultiOutPipeline
-from multipipe import CombMultiInPipeline, InputPriorityArbiter
+from multipipe import PriorityCombMuxInPipe
 
 #from fpbase import FPNumShiftMultiRight
 
@@ -1910,15 +1910,6 @@ class FPADDBasePipe(ControlBase):
         return m
 
 
-class PriorityCombPipeline(CombMultiInPipeline):
-    def __init__(self, stage, p_len):
-        p_mux = InputPriorityArbiter(self, p_len)
-        CombMultiInPipeline.__init__(self, stage, p_len=p_len, p_mux=p_mux)
-
-    def ports(self):
-        return self.p_mux.ports()
-
-
 class FPAddInPassThruStage:
     def __init__(self, width, id_wid):
         self.width, self.id_wid = width, id_wid
@@ -1927,13 +1918,11 @@ class FPAddInPassThruStage:
     def process(self, i): return i
 
 
-class FPADDInMuxPipe(PriorityCombPipeline):
+class FPADDInMuxPipe(PriorityCombMuxInPipe):
     def __init__(self, width, id_width, num_rows):
         self.num_rows = num_rows
         stage = FPAddInPassThruStage(width, id_width)
-        PriorityCombPipeline.__init__(self, stage, p_len=self.num_rows)
-        #self.p.i_data = stage.ispec()
-        #self.n.o_data = stage.ospec()
+        PriorityCombMuxInPipe.__init__(self, stage, p_len=self.num_rows)
 
     def ports(self):
         res = []
diff --git a/src/add/test_inout_mux_pipe.py b/src/add/test_inout_mux_pipe.py
index 36c4d991..c30ba644 100644
--- a/src/add/test_inout_mux_pipe.py
+++ b/src/add/test_inout_mux_pipe.py
@@ -1,4 +1,4 @@
-""" key strategic example showing how to do multi-input fan-in into a 
+""" key strategic example showing how to do multi-input fan-in into a
     multi-stage pipeline, then multi-output fanout.
 
     the multiplex ID from the fan-in is passed in to the pipeline, preserved,
@@ -12,20 +12,10 @@ from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
 from multipipe import CombMultiOutPipeline
-from multipipe import CombMultiInPipeline, InputPriorityArbiter
+from multipipe import PriorityCombMuxInPipe
 from singlepipe import UnbufferedPipeline
 
 
-class PriorityCombPipeline(CombMultiInPipeline):
-    def __init__(self, stage, p_len):
-        p_mux = InputPriorityArbiter(self, p_len)
-        CombMultiInPipeline.__init__(self, stage, p_len=p_len, p_mux=p_mux)
-
-    def ports(self):
-        return self.p_mux.ports()
-        #return UnbufferedPipeline.ports(self) + self.p_mux.ports()
-
-
 class MuxCombPipeline(CombMultiOutPipeline):
     def __init__(self, stage, n_len):
         # HACK: stage is also the n-way multiplexer
@@ -66,7 +56,7 @@ class PassThroughStage:
         return PassData()
     def ospec(self):
         return self.ispec() # same as ospec
-                
+
     def process(self, i):
         return i # pass-through
 
@@ -160,11 +150,11 @@ class InputTest:
         print ("recv ended", mid)
 
 
-class TestPriorityMuxPipe(PriorityCombPipeline):
+class TestPriorityMuxPipe(PriorityCombMuxInPipe):
     def __init__(self, num_rows):
         self.num_rows = num_rows
         stage = PassThroughStage()
-        PriorityCombPipeline.__init__(self, stage, p_len=self.num_rows)
+        PriorityCombMuxInPipe.__init__(self, stage, p_len=self.num_rows)
 
     def ports(self):
         res = []