From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 10 Jul 2020 08:44:27 +0000 (+0100)
Subject: cut/paste error writing to wrong vcd file
X-Git-Tag: div_pipeline~114
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5ad31143b8e3222b91ec86c2294bbcea90ad03d9;p=soc.git

cut/paste error writing to wrong vcd file
---

diff --git a/src/soc/fu/mul/test/test_pipe_caller.py b/src/soc/fu/mul/test/test_pipe_caller.py
index cda81076..44f5a09e 100644
--- a/src/soc/fu/mul/test/test_pipe_caller.py
+++ b/src/soc/fu/mul/test/test_pipe_caller.py
@@ -215,7 +215,7 @@ class TestRunner(FHDLTestCase):
                     yield Settle()
 
         sim.add_sync_process(process)
-        with sim.write_vcd("div_simulator.vcd", "div_simulator.gtkw",
+        with sim.write_vcd("mul_simulator.vcd", "mul_simulator.gtkw",
                             traces=[]):
             sim.run()