From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 2 Jun 2020 20:57:28 +0000 (+0100)
Subject: oooo very annoying.  there does not appear to be any difference between two set_input... 
X-Git-Tag: div_pipeline~637^2~31
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5ad6f8a505ae13f5a864a82f4f484015c1766ecc;p=soc.git

oooo very annoying.  there does not appear to be any difference between two set_inputs functions
---

diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index 704cd7f9..493e7242 100644
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -118,7 +118,7 @@ class BranchTestCase(FHDLTestCase):
                                      initial_sprs=initial_sprs,
                                      initial_cr=cr)
 
-        
+
 
     def test_ilang(self):
         pspec = BranchPipeSpec(id_wid=2)
@@ -227,33 +227,48 @@ class TestRunner(FHDLTestCase):
         # CIA (PC)
         res['cia'] = sim.pc.CIA.value
 
-        # CR A
-        cr1_en = yield dec2.e.read_cr1.ok
-        if cr1_en:
-            cr1_sel = yield dec2.e.read_cr1.data
-            res['cr_a'] = sim.crl[cr1_sel].get_range().value
-
         # Fast1
         spr_ok = yield dec2.e.read_fast1.ok
-        spr_num = yield dec2.e.read_fast1.data
-        # HACK
-        spr_num = fast_reg_to_spr(spr_num)
         if spr_ok:
-            res['spr1'] = sim.spr[spr_dict[spr_num].SPR].value
+            fast1_sel = yield dec2.e.read_fast1.data
+            # HACK
+            spr_num = fast_reg_to_spr(fast1_sel)
+            res['spr1'] = sim.spr[spr_num].value
 
         # SPR2
         spr_ok = yield dec2.e.read_fast2.ok
-        spr_num = yield dec2.e.read_fast2.data
-        # HACK
-        spr_num = fast_reg_to_spr(spr_num)
         if spr_ok:
-            res['spr2'] = sim.spr[spr_dict[spr_num].SPR].value
+            fast2_sel = yield dec2.e.read_fast2.data
+            # HACK
+            spr_num = fast_reg_to_spr(fast2_sel)
+            res['spr2'] = sim.spr[spr_num].value
+
+        # CR A
+        cr1_en = yield dec2.e.read_cr1.ok
+        if cr1_en:
+            cr_sel = yield dec2.e.read_cr1.data
+            res['cr_a'] = sim.crl[cr_sel].get_range().value
 
         print ("get inputs", res)
         return res
 
     def set_inputs(self, branch, dec2, sim):
-        yield branch.p.data_i.spr1.eq(sim.spr['CTR'].value)
+        print(f"cr0: {sim.crl[0].get_range()}")
+
+        inp = yield from self.get_inputs(dec2, sim)
+
+        if 'spr1' in inp:
+            yield branch.p.data_i.spr1.eq(inp['spr1'])
+        if 'spr2' in inp:
+            yield branch.p.data_i.spr2.eq(inp['spr2'])
+        if 'cr_a' in inp:
+            cr_sel = yield dec2.e.read_cr1.data
+            cr = inp['cr_a']
+            yield branch.p.data_i.cr.eq(cr_sel)
+            full_cr = sim.cr.get_range().value
+            print(f"full cr: {full_cr:x}, sel: {cr_sel}, cr: {cr:x}")
+
+    def set_inputs(self, branch, dec2, sim):
         print(f"cr0: {sim.crl[0].get_range()}")
 
         # TODO: this needs to now be read_fast1.data and read_fast2.data