From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 12 Sep 2022 15:26:28 +0000 (+0100)
Subject: add rudimentary sv.setvl unit test to just check that the syntax
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5ae1f84b516533e464532092f2e87b0e83db8c3a;p=openpower-isa.git

add rudimentary sv.setvl unit test to just check that the syntax
is correct.  going beyond RT=0..31 currently fails
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 757527c4..9b1ba07f 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -363,7 +363,7 @@ def get_pdecode_idx_in(dec2, name):
     log("get_pdecode_idx_in FRC in3", name, in3_sel, In3Sel.FRC.value,
         in3, in3_isvec)
     # identify which regnames map to in1/2/3
-    if name == 'RA':
+    if name == 'RA' or name == 'RA_OR_ZERO':
         if (in1_sel == In1Sel.RA.value or
                 (in1_sel == In1Sel.RA_OR_ZERO.value and in1 != 0)):
             return in1, in1_isvec
@@ -470,6 +470,8 @@ def get_pdecode_idx_out(dec2, name):
             dec2.dec.RT)
         if out_sel == OutSel.RT.value:
             return out, o_isvec
+        if out_sel == OutSel.RT_OR_ZERO.value and out != 0:
+            return out, o_isvec
     elif name == 'RT_OR_ZERO':
         log("get_pdecode_idx_out", out_sel, OutSel.RT.value,
             OutSel.RT_OR_ZERO.value, out, o_isvec,
diff --git a/src/openpower/decoder/isa/test_caller_setvl.py b/src/openpower/decoder/isa/test_caller_setvl.py
index 0f25218b..542e652b 100644
--- a/src/openpower/decoder/isa/test_caller_setvl.py
+++ b/src/openpower/decoder/isa/test_caller_setvl.py
@@ -262,6 +262,43 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(CR0[CRFields.GT], 1)
             self.assertEqual(CR0[CRFields.SO], 1)
 
+    def test_sv_sv_setvl(self):
+        """test sv.setvl instruction works.  WARNING, going beyond
+        RT=0..31 does not work, bug in PowerDecoder2 / ISACaller,
+        related to RT_OR_ZERO and to simplev.mdwn pseudocode having
+        _RT not be EXTRA-extended properly
+        """
+        lst = SVP64Asm(["sv.setvl 8, 31, 10, 0, 1, 1", # setvl into RT=8
+                        ])
+        lst = list(lst)
+
+        # SVSTATE (in this case, VL=4) which is going to get erased by setvl
+        svstate = SVP64State()
+        svstate.vl = 4 # VL
+        svstate.maxvl = 4 # MAXVL
+        print ("SVSTATE", bin(svstate.asint()))
+
+        initial_regs = [0] * 64
+        initial_regs[31] = 200
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, initial_regs=initial_regs,
+                                                svstate=svstate)
+            print ("SVSTATE after", bin(sim.svstate.asint()))
+            print ("        vl", bin(sim.svstate.vl))
+            print ("        mvl", bin(sim.svstate.maxvl))
+            print ("    srcstep", bin(sim.svstate.srcstep))
+            print ("    dststep", bin(sim.svstate.dststep))
+            print ("     vfirst", bin(sim.svstate.vfirst))
+            self.assertEqual(sim.svstate.vl, 10)
+            self.assertEqual(sim.svstate.maxvl, 10)
+            self.assertEqual(sim.svstate.srcstep, 0)
+            self.assertEqual(sim.svstate.dststep, 0)
+            self.assertEqual(sim.svstate.vfirst, 0)
+            print("      gpr31", sim.gpr(31))
+            print("      gpr8", sim.gpr(8))
+            self.assertEqual(sim.gpr(8), SelectableInt(10, 64))
+
     def test_svstep_1(self):
         lst = SVP64Asm(["setvl 0, 0, 10, 1, 1, 1", # actual setvl (VF mode)
                         "setvl 0, 0, 1, 1, 0, 0", # svstep